Clocking of ADC12J4000

Hi Tony

We're looking into this request and will respond as soon as possible.

Best regards,

Jim B

Hi Tony

You have recognized the challenge to clocking this JESD204B data converter. For applications needing clock rates above 3.08 GHz a two-chip clocking solution is needed (at minimum).

For systems using 2 or 3 ADCs, one TRF3765 can be used along with an LMK04828 to provide all needed device and SYSREF clocks. For single ADC systems the LMX2582 is also a good choice for the clock synthesizer.

For systems needing more than 3 ADCs a different approach must be taken.

Can you describe the number of ADC12J4000s (at 4 GHz), along with the number of other converters/DACs and their required clock frequencies? This information plus the number of FPGAs in the system will help me recommend a clocking architecture that will meet those needs.

Best regards,

Jim B

Hi Jim,

Yes, I've run into the wall - glad to know it's not just me.

I plan to clock 4 ADC12J4000s at 4 GHz, no other DACs/ADC's at present, and all going into 1 FPGA.

The TRF3765 is a fine chip but its closed loop phase noise (for example Figure 47 in the data sheet) is about 400 fs at 3.5 GHz and that will eat almost 1 ENOB off the resolution of the ADC12J4000.

So I have come to the same architecture you are suggesting: Use the LMK04828 for clocking at frequencies up to 3 GHz, then switch over to a (low noise) VCO driven by a PLL locked to one of the LMK04828 outputs - and split 4 ways - for clocks up to 4 GHz.

In this scheme the LMK04828 always provides the SYSREF (and I think SYNC/TMST) signals to all the ADC'12J4000's. Then for operation at or under 3 GHz it also provides the DEVCLK inputs. However, for operation above 3 GHz the DEVCLK's switch over to a VCO/PLL combination that is, of course, locked to the LMK04828, which is now tuned to operate at exactly half the clock rate of the VCO/PLL - so, for example, the LMK's outputs run at 2 GHz if the VCO/PLL output driving the DEVCLK pins is at 4 GHz.

Do you see any problems with this scheme?

Of course if TI is planning to release an upgrade to the LMK04828 that goes to 4 GHz it would save a lot of complexity, cost, real estate, power, etc - in short the world would be a better place. So Jim, please tell us that TI will be doing this soon.

Thank you.

Hi Tony

There aren't any 4 GHz output capable LMK04828-like devices planned.

Your approach sounds reasonable. Another PLL/VCO to consider is the recently released LMX2582. But it only has 2 outputs so you'll need to add clock fan-out to support a 4 ADC system.

The next priority after minimizing jitter in the ADC DEVCLK is in minimizing the DEVCLK to SYSREF skew variation over temperature. The ADC12J4000 has features that allow it to work with any arbitrary DEVCLK to SYSREF skew, but if the skew changes significantly with temperature the RDEL setting may need to be adjusted as a function of temperature.

Hope this helps.

Best regards,

Jim B

Hello,
If use LMX2582 and LMK04828 for clocking adc12J4000, what is the most preferred scheme: a) LMX2582 after LMK04828 (DClkout LMK is refclk for LMX) or b) LMK04828 (in distribution mode) after LMX2582? And whether the outputs LMX to set different dividers: 4GHz to DEVClk ADC and 2GHz to LMK for generate SYSREF?
In system 1 ADC12J4000 only.

Thank you

Hi Lee

The best choice for clocking scheme depends on a few different factors. If the ADC DEVCLK frequency needs to be quite flexible and the LMK04828 VCO range will not allow the needed FPGA or SYSREF frequencies to be generated, then I would choose b). In this scheme I would recommend using an external board level divide-by-2 to create the DEVCLK/2 frequency sent to the LMK04828. If the internal LMX2582 divider is used, internal crosstalk from the /2 clock to the full rate ADC DEVCLK will occur, which will show up in the ADC spectrum as an Fs/2-Fin spur.

If you need to synchronize multiple ADCs and the LMK04828 VCO range is acceptable to generate the needed SYSREF and FPGA clock frequencies, then the a) scheme will be better. You can use the LMK04828 DCLKout as the reference to an LMX2582 which can clock 2 ADC12J4000 devices. You could support additional ADCs by adding more LMX2582 devices.

Best regards,

Jim B

Hi Jim,

Thank You for reply.