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ADS4245EP

srikanth adkewar
Prodigy 190 points

I am using ADS4245EP in my application.

Single ended clock, 0.1uF coupled to CLKP and VCM connected to CLKM using decoupling capacitor of 0.01uF .Sampling freq:15MSPS.parallel CMOS 2's complement mode.clock input: 1.8V LVCMOS square wave.

In this mode of operation ADC does not start.

when VCM is not loaded ADC starts working.But, it keeps drawing very high currents(340mA-240mA).This current keeps changing every time I power up the device.

Please check the VCM circuitry with the ADC designers.I have seen similar complaints in the forum regarding VCM loading.

also, Is there any sequencing of power required for AVDD and DRVDD .

  • 0
    TI__Guru* 91947 points

    Srikanth,

    What are you driving with the VCM? Are you setup for parallel SPI mode? What levels are SEN, SCLK, CTRL1-3 and RESET?

    Regards,

    Jim

  • 0 in reply to jim s
    Prodigy 190 points
    I am trying to use parallel CMOS interface 2' complement output mode.reset,sclk are high.sen and sdata is low.VCM is connected to CLKM and transformer circuit for differential input as given in datasheet.cntr1-3:101. channel A powerdown and channel B active.
  • 0 in reply to srikanth adkewar
    TI__Guru* 91947 points

    Srikanth,

    The design team is looking into this issue. We hope to have an answer in the near future.

    Regards,

    Jim

  • 0 in reply to jim s
    Prodigy 190 points
    Hello Jim,
    Any reply from the design team regarding this issue?
    please let me know.

    Regards,
    A.Sreekanth
  • 0 in reply to srikanth adkewar
    TI__Guru* 91947 points

    Srikanth,

    We suspect there is some (unwanted) termination from CTRL pins or SPI pins to ground in your design and the Marketing EVM as it also draws more current after power up in some cases. This termination may be causing excess amount of current when forcing a DC voltage on these pins. Below are test results from the design team:

     

    In our testing today, device functions perfectly fine and is in accordance with the datasheet description.

    See the quick results below:

     

     

    Current, mA

    Voltage on Pins 

    Logic level

     

     

    FS,MSPS

    AVDD

    DRVDD

    Board_Supply

    Reset

    SEN

    SCLK

    SDATA

    CTRL1,2,3

    VCM

    Resulting Mode

    15

    49

    16

    8

    0

    1.8

    0

    0

    0,0,0

    0.95

    LVDS(2s Cmp)

    15

    33

    13

    8

    0

    1.8

    0

    0

    1,0,1

    0.96

    LVDS(2s Cmp)

    15

    33

    13

    8

    1.8

    1.8

    1.8

    0

    1,0,1

    0.96

    LVDS(2s Cmp)

    15

    32

    5

    8

    1.8

    0

    1.8

    0

    1,0,1

    0.96

    CMOS, (2s Cmp)

    Regards,

    Jim