why does SINAD decrease with input frequency ?

Pankaj,

Most broadband circuits suffer from worse distortion at higher frequencies. It all depends on how the circuit was designed, but most transistor-based "linear" analog circuits must use some form of linearization technique (high gain feedback as an example). Those techniques usually have limited bandwidth, so the overall circuit distortion gets worse as the signal goes outside the bandwidth of the linearization technique. Non-linear parasitics (like junction capacitances) can also impact the distortion at higher frequencies. This all impacts the THD.

There generally is no equation that relates THD to frequency. It's all circuit dependent.

At higher frequencies, SINAD may also get worse, but for another reason. SINAD contains noise interference. At higher frequecies, clock jitter impacts the noise performance more than at low frequencies. You can read up on the effects of clock jitter on ADC performance where you'll find equations for the simple relationship between SNR and jitter.

Regards, Josh

Hi,

Actually, both SNR and SINAD get worse with increasing input frequency.  (SNR is signal to noise ratio where the noise is all of the noise floor of the FFT summed up excluding the harmonics.  SINAD is also signal to noise ratio, but the difference is the noise is all of the noise floor of the FFT summed up including the harmonics.)  THD does not generally get worse with increasing frequency for purposes of this discussion. 

The formula you ask for is equation 3 in that same document, along with figure 12 to illustrate that equation.   Equation 3 says that as your clock jitter increases your SNR gets worse - this makes sense because if your clock edge is in the wrong spot then you won't get quite the right sample that you were looking for.   But equation 3 also has input frequency as part of that equation right along with clock jitter.    In figure 12 the downward slope of the plots show that as input frequency increases SNR (and SINAD) will decrease.

Figure 13 goes further to illustrate why.  As I mentioned, if there is clock jitter then there will be error in the sample because of the error in the placement of the clock edge.  but in a higher frequency input, the slope of the input signal is steeper so for the same amount of error in clock edge placement there is more error in the sample for high frequency input than there would be for low frequency input.  More error in the sample means lower SNR and lower SINAD.

Regards,

Richard P.