TSW1200EVM Board: FPGA Configuration File and UART-USB-Bridge

Simon D.

Other Parts Discussed in Thread: TUSB3410, ADS6445, ADS62P49, ADS5400, FMC-ADC-ADAPTER, ADS5474, ADS5485, ADS5560, ADS62P24

Hello!

I have the TSW1200EVM module and use it to develope a measurement system with the high speed ADC 62P49. The FPGA boot prom contains two fpga configurations to drive different ADC evaluation boards.

Is it possible to get the Xilinx ISE project and *.bit files of these two configurations?

Furthermore I'd like to use the UART - USB bridge that is realized with the TUSB3410 Chip. The configuration to drive the board with the Ti software is stored in the I2C EEPROM named U8.

Can somebody tell me how this program in the I2C EEPROM configures the TUSB3410 (how many bits, baudrate, stoppbits, parity)?

Regards Simon

over 15 years ago

0 Richard Prentice over 15 years ago

TI__Mastermind 29220 points

Hi,

There are two bit files stored in the eeprom for the FPGA, but one of these bit files is for the parallel LVDS DDR format such as you need for your ADS62P49 and the other bit file is for devices that have serialized data lines such as for ADS6445.

If you provide an email address, i can send the bit file and the Verilog source code for the parallel LVDS DDR data format. Please understand that while we supply the source code upon request, we must state that the code was not developed with public support in mind and is not documented and commented for public use and support. The code is to be taken 'as-is'. If this is acceptable, then i can email you the code. The zip file for the source code includes all the Verilog files, the ucf file, and the ngc files for the memory blocks. Everything is there to make the project. (The actual ISE project is far too large to email.)

The UART function is used to transfer data to and from the FPGA to the USB chip, and as you will see in the FPGA code is a simple RX UART and TX UART that was downloaded from the FPGA Vendor's website. A simple 8bit UART, and i do not know the exact parameters of its use. The baudrate for the UART may be 115200KBaud, 230400KBaud, or 460800KBaud. There is an option for 921600KBaud, but this is error-prone. The USB chip as you have noticed is the TUSB3410, and for this we use the VCP Virtual Com Port installation tools taken from the TI web site for that product, and the firmware for the TUSB3410 is a standard .i51 file that we also used directly from the USB group. The only thing that we have to program into the small eeprom for the USB chip is the text string for the TSW1200 Capture Card, the Vendor unique ID number, the Product ID number, and that the firmware is to be loaded from the PC at instantiation time rather than from eeprom. The firmware for the USB chip is not stored in eeprom, but rather is the umpf3410.i51 file that is installed under Windows\system32\drivers folder upon installation of the TSW1200 and virtual com port.

Regards,

Richard P.

0 Simon D. over 15 years ago in reply to Richard Prentice

Prodigy 200 points

Hello!

Thank you for your fast answer and good informations... I will have a look at the files you will send me....

My email address is: s.darsch@lmt.uni-saarland.de

Regards

S. Darsch

0 Richard Prentice over 15 years ago in reply to Simon D.

TI__Mastermind 29220 points

Hi,

The requested information has been emailed.

Regards,

Richard P.

0 Alexandru Burcea over 15 years ago in reply to Richard Prentice

Prodigy 150 points

Hi,

I have 2xTSW1200evm and 2xADS61B29, I need to read the 2's ADC sincrhonus.

I download the ISE project files(from Xilinx) and I think are incomplete (USART module missing).

It is possible to get compelte FPGA source code and support for what I try to do ? (alex@digitech.ro)

Regards,

Alex.

0 Simon D. over 15 years ago in reply to Alexandru Burcea

Prodigy 200 points

Hi,

I just sent you an email...

Regards Simon

0 Alexandru Burcea over 15 years ago in reply to Simon D.

Prodigy 150 points

Hi,

Something is happening with my mail server, I receive your mail but I ken't answer. (I write my answer here)

>
> I need to have separate boards, I use onboard VCXO clock option for ADC
> and provide the same 20MHz ref clock. I need the same time skew between
> ADC's for multiple buffers .
> I whant to change FPGA config to make continus aquisition (read 1 buffer
> then whait a fix number of samples and start read again ...)
> For reading the ADC I use on TSW1200evm "PROM LOAD" CFG1 12bits LVDS
> Please send me a source code for FPGA (current version of dev-kit) and I
> will modify to fit my application (hope).
>
>

Thanks,
Alex.

0 Alexandru Burcea over 15 years ago in reply to Alexandru Burcea

Prodigy 150 points

Hi,

I have install the ISE but what shuld do with the dat file ?

I don't see vhdl or verilog souece code, I miss something?

Sorry for bugging you.

Regards,

Alex.

0 Alexandru Burcea over 15 years ago in reply to Alexandru Burcea

Prodigy 150 points

Hi,

Where are this files, you send me only "ATT00562.dat".

Regards,

Alex.

0 Alexandru Burcea over 15 years ago in reply to Alexandru Burcea

Prodigy 150 points

Hi,

Thank you for the files and good information.

Regards,

Alex.

0 Danh Nguyen over 15 years ago in reply to Alexandru Burcea

Prodigy 40 points

Hello,

I am working on interfacing the ADS5400 to Xilinx Virtex 6 FPGA using the FMC-ADC-ADAPTER card. Can you please give me access to the source code for handling parallel LVDS signal outputs as being done in the TSW1200 firmware for reference.

I would really appreciate your help in this matter. My email address is: danhnguyen04@gmail.com

Thank you and best regards,

Danh.

0 Richard Prentice over 15 years ago in reply to Danh Nguyen

TI__Mastermind 29220 points

A zip file of the code has bent to the email address provided.

Regards,

Richard P.

0 James Gibbs over 15 years ago in reply to Richard Prentice

Prodigy 30 points

I am also working on interfacing the ADS5400 evaluation board with a virtex 6 through the FMC connector and would really appreciate the source code (jgibbs AT segmail.com).

At lower frequencies (500MSPS and below), I have no problems, but I start to get what appear to be single bit errors as the frequency increases to around 600+ MSPS.

I am using the dual channel SDR LVDS setting, and my timing constraints all pass @ 500MHz per channel (which should support up to 1GSPS).

When I run the test output mode on the ADC (switch between all x"000" and x"FFF") I see single bit errors show up at higher frequencies (that should be well within my what my timing analysis shows working).

0 Richard Prentice over 15 years ago in reply to James Gibbs

TI__Mastermind 29220 points

Sent, as requested, with the following text:

As requested, here are our Verilog files for the TSW1200 firmware source, along with the ucf file and the ngc files for blocks like the memory.

I am using dual channel, but not SDR (as in figure2 in the datasheet). I am using dual bus DDR, (as in figure 4 in the datasheet) and letting the IDDR cell catch the data on a delayed (IDELAY) rising and falling edge. But I should be able to run the Virtex4 with single bus DDR, as the advertised rate of the DDR input is 1000Msps. But since the memory in my FPGA is limited to 250MHz, I let the ADC give me a divide by 4 CLKOUT anyway, and so I use dual bus mode.

Regards,

Richard P

0 Simon D. over 15 years ago in reply to Richard Prentice

Prodigy 200 points

Hi Richard ,

This time I was about one minute faster than you - I already sent the data per mail...

But I have another question concerning the clock. As you wrote, you are interfacing the adcs with idelays and iddrs like the picture below... My problem is, that the clock that comes out of a BUFR is only a regional clock - so I receive a error if i set the fifo size to the maximum - because then I need a global clock...

The question to you is, how did you solve this problem in the TSW1200 configuration?

Regards Simon

0 litao yan over 15 years ago in reply to Richard Prentice

Prodigy 60 points

Hi ,

Can I have the source code for my reference,I use the ads6445 for my design , the bit file and the Verilog source code for the parallel LVDS DDR data format are very well for my reference

email yanlitao122@126.com

regards,

tao

0 Simon D. over 15 years ago in reply to litao yan

Prodigy 200 points

A zip file of the code has bent to the email address provided.

Regards,

Simon

0 litao yan over 15 years ago in reply to Simon D.

Prodigy 60 points

thanks

0 Tom Soyer over 14 years ago in reply to Richard Prentice

Prodigy 20 points

Hi Richard,

I am trying to connect the ADS5474 EVM board,DAC5682z EVM and ML605 using Adc/DAC-FMC adapters.,and met some hurdles.

Could you send me the verilog code samples to email address (zztt04@yahoo.com)?

Thanks and best regards,

Tom

0 Richard Prentice over 14 years ago in reply to Tom Soyer

TI__Mastermind 29220 points

Hi,

We do not have Verilog code for the ML605 development platform, if that is what you mean by 'Verilog code samples'.

What i do have is the source code for how we interface the ADS5474 to the Virtex4 that is on the TSW1200, using the IDDR input cell and the IDELAY cell to adjust the timing to meet setup and hold time into the IDDR. The IDELAY settings would be different for a Virtex6, and the contraint file would be different for the different pin assignment that you would find for the routing into the Virtex6 through the FMC adapter card. And the interface after the IDDR will be more complicated that you need because the TSW1200 has to support so many different ADC data formats. But i can send this database to you.

Regards,

Richard P.

0 Tom Soyer over 14 years ago in reply to Richard Prentice

Prodigy 20 points

Thanks alot.

0 Carolin Loibl over 14 years ago in reply to Tom Soyer

Prodigy 40 points

Hallo ,

i would also need the sourcecode ( verlog and bit file) for my reference. I use TSW1200 with AD5282.

My email: c.loibl@tum.de

Thanks

Carolin Loibl

0 Richard Prentice over 14 years ago in reply to Carolin Loibl

TI__Mastermind 29220 points

sent by email.

Regards,

Richard P.

0 xiao Ai over 14 years ago in reply to Richard Prentice

Prodigy 10 points

Hi Richard,

I am a bristol univeristy research student, we will soon receive the TSW1200 and ADS5485. May I have the Xilinx ISE files (VHDL etc.) for studying.Thanks very much for your support. My email address is: rossai2001@hotmail.com

Xiao

0 Richard Prentice over 14 years ago in reply to xiao Ai

TI__Mastermind 29220 points

Hi,

Verilog source files sent by email.

Regards,

RIchard P.

0 Zakhar Lifshits over 14 years ago in reply to Richard Prentice

Prodigy 20 points

Hi Richard,

In my new design I am going to interface ADS5560 to Spartan 6. Could you send me the Verilog code for TSW1200 to my email (lizakarn@gmail.com) so I can use it as a reference?

Thanks a lot.

Zak.

0 Zakhar Lifshits over 14 years ago in reply to Richard Prentice

Prodigy 20 points

Hi Richard,

In my new design I am going to interface ADS5560 to Spartan 6. Could you send me the Verilog code for TSW1200 to my email (lizakarn@gmail.com) so I can use it as a reference?

Thanks a lot.

Zak.

0 Richard Prentice over 14 years ago in reply to Zakhar Lifshits

TI__Mastermind 29220 points

Sent to the address provided.

Regards,

Richard P.

0 JIN LI over 14 years ago in reply to Richard Prentice

Prodigy 90 points

Hi Richard,

I am using TSW1200EVM with ADS62p24. Could you please send me the TSW1200 FPGA sourcecode ( verlog and bit file) for my reference?

My email: lijin_1@hotmail.com

Thanks and best regards,

Jin

0 Richard Prentice over 14 years ago in reply to JIN LI

TI__Mastermind 29220 points

Sent to the address provided.

As a note to those who find these requests for the source code and also wish to request them, it may be safer to enter a new posting than to append to a previous posting. Once a thread on this forum is marked as answered, I may not see the appended request if I just look through the forum for unanswered postings that need my attention. So if I don't see the appended request at the time it gets appended, I may miss seeing it later and the request might not get fulfilled.

Regards,

Richard P.

0 luc albarede over 13 years ago in reply to Richard Prentice

Prodigy 20 points

Hi Richard,

I am evaluating the ADS62P49 with TSW1200 for 2 channels at the same time,

could you send me the code for TSW1200EVM with ADS62P49? matlab and FPGA.

thanks in advance,

luc.albarede@gmail.com

0 Richard Prentice over 13 years ago in reply to luc albarede

TI__Mastermind 29220 points

Hi,

Sent to the address provided.

Regards,

Richard P.

0 Richard Prentice over 13 years ago in reply to luc albarede

TI__Mastermind 29220 points

Sent to the address provided.

Regards,

Richard P.

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TSW1200EVM Board: FPGA Configuration File and UART-USB-Bridge