This is a question about what seems like a discrepancy between SYSREF calculated and SYSREF setup by the DAC37J84 GUI
My DAC37J84EVM card uses LMF = 841, K =20
Refering to the DAC 3XJ8X GUI v1.1, Quick Start page:
Clocking mode = Onboard
Device = DAC37J84
DAC Data input ate = 983.04 Msps
Number of SERDES lanes = 8
Interpolation = 1
DAC otuput rate = 983.04 Msps
FPGA Clock = 256.76 MHz
JESD204 Mode = 8411
SERDES Line rate = 9830.4 Mbps
The LMK40828 PLL2, VCO1 freuency is:
prescaler*Ndivider*OSCin = 2*12*(122.88) = 2949.1MHz
PLL1 does not lock, PLL2 does lock up. The DAC PLL is not used
On the page "LMK04828 Controls -> SYSREF and SYNC, I see
SYSREF Source = SYSREF Pulses
SYSREF Divider = 160
Pulse Count = 8
So does this mean the SYSREF frequency is: 2949.1/160 = 18.4319 MHz?
If so, then why does the formula:
SYSREF = (SERDES line rate)/(10*n*F*K) = 9830.4/(10*n*1*20) = 49.1520 MHz for n=1
SYSREF = (SERDES line rate)/(10*n*F*K) = 9830.4/(10*n*1*20) = 24.5760 MHz for n=2
SYSREF = (SERDES line rate)/(10*n*F*K) = 9830.4/(10*n*1*20) = 16.3840 MHz for n=3
Not match up with 18.4319 MHz?
Thanks very much,
John Reyland
