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TVP5150AM1 I2C Timing

Qiang Liu
Prodigy 20 points
Other Parts Discussed in Thread: TVP5150

Hi

    From the spec, I found that TVP5150 needs some delay before the master sending stop condition.

    While I measured that TVP5150 pulled the SCL line low after it sending ACK, that caused the master would read wrong data.

    Please help us to check it .Thanks

  • 0
    Intellectual 290 points

    Dear Mr.liu

       Datasheet  3.18.2.2:

    The TVP5150 device requires delays in the I2C accesses to accommodate its internal processor’s timing. In
    accordance with I2C specifications, the TVP5150 device holds the I2C clock line (SCL) low to indicate the wait
    period to the I2C master. If the I2C master is not designed to check for the I2C clock line held-low condition,
    then the maximum delays must always be inserted where required. These delays are of variable length;
    maximum delays are indicated in the following diagram:
    Normal register writing address 00h−8Fh (addresses 90h−FFh do not require delays)

     

    So you can add 64us dealy after every ACK (not only the data ACK ) and try it again.

    Thx.

  • 0 in reply to qiang xiang
    Prodigy 20 points
    Hi

    Thanks for the last reply .
    Now I have set TVP5150 regs as ( 03 : 0dh , 04 : c0h , 0d : 40h) and left other regs as default value , while my review picture is all magenta.
    How could I modify the reg setting?