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ADS5401 clock input range and performances

Antoine Chapelain
Prodigy 20 points
Other Parts Discussed in Thread: ADS5401, LMK04906

Hello,

I am working with the ADS5401 high-speed data converter. The nominal sampling clock provided to the ADS5401 is a 800 MHz clock generated by the TI LMK04906. The performances of the ADS with a 800 MSPS sampling rate correspond to what we need for our purpose. We have a need to use different clock frequencies, for instance 40 MHz (provided by the same clock synthesizer).


I know that 40 MSPS is the lower limit for the digitization rate (800 MSPS being the upper limit). The performances of the ADS with a 40 MSPS sampling rate is not as good. In particular, looking at the ADS intrinsic noise I observe than the noise shows two distributions, meaning that the noise is going back and forth between two offset values. This behaviour is not seen at all for frequencies above 100 MHz, up to 800 MHz. I am attaching slides (hope it's going to work) to this post to show you the noise problem I am facing, the 800 MHz clock signal, 40 MHz clock signal.

slides.pdf

Does the ADS5401 needs a sine wave clock only or is a square wave fine too? The shape of the signal output by the clock synthesizer is changing from a nice sine wave at 800 MHz to a square looking wave at 40 MHz. Could it be an issue? The amplitude of the clock are also different but I do not see why it would be an issue according the ADS data sheet.


Thanks in advance for you help!

Antoine.

  • 0
    TI__Mastermind 29220 points

    Hi,

    I apologize for the delay.  I am able to see the slides you attached.

    I do not have any data to corroborate or not corroborate the dual distribution of the idle-channel codes for such a low sample rate.  Looking through the datasheet I see ADC performance at anything other than 800Msps is only down to 300Msps in the contour plots of SNR and SFDR.

    The shape of the sample clock edge should not, in general, be an issue.  The ADC is looking for the rising edge of the clock, and in theory a sharper edge would be better as would be the case with a square wave clock.    All of our device characterization is done with a sine wave clock however, because even the best lab signal generators do not have low enough phase noise to match the aperture jitter of the ADC itself, and we use narrow bandpass filters to remove as much phase noise from the clock as we can.  And bandpass filters turn even a square wave clock into a sine wave clock by removing harmonics as well as the rest of the phase noise.    But even then we see larger amplitude clocks lead to better AC performance primarily due to sharper edge rate. 

    Hmmm, you mention the two observed offset values, and that reminds me that the ADC is itself internally constructed as a 2-way interleaved device.  see the block diagram in section 8.2 of the datasheet.  Each of these two sub-ADCs will have its own offset and gain error, and there is digital logic to adjust the offset of each sub ADC and the gain of each sub ADC.   Are you using the device with auto correction enabled?  If you turn off autocorrection, do you see more of a spread in distribution or perhaps the numbers of samples in each distribution equalize?  

    I suspect you are seeing an artifact of the correction logic for the 2-way interleaving.  As an experiment, for the 40Msps case - if you were to bump the clock back up to 80Msps and then just 'throw away' every other sample to cut the sample rate back down to 40Msps, do you see the dual distribution disappear?

    Regards,

    Richard P.