Dear specialists,
Please let me ask you a question about the ADC124S051.
The following description is described on the data sheet page 18.
"If CS and SCLK go low within the times defined by tCSU and tCLH,
the rising edge of SCLK that begins clocking in data at DIN may
be one clock cycle later than expected. It is, therefore, best to
strictly observe the minimum tCSU and tCLH times given in the
Timing Specifications."
I infer that the above description is described for the case of the
falling edge of CS and the rising edge of SCLK are present within
the times defined by tCSU and tCLH.
*Cf. attached file waveforms3.xlsx
I understand that even if the falling edge of CS and the falling edge of SCLK
are present near,the rising edge of SCLK that begins clocking in data at DIN
is never delayed one clock cycle later than expected.
*Cf. attached file waveforms3.xlsx
Is my understanding correct?
Best regards.
Tsuyoshi Tokumoto
