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Observing incorrect FPGA Clock and DAC Clock frequencies in DAC39J84 when External Clocking Mode is used.

Syed Shafi
Prodigy 65 points
Other Parts Discussed in Thread: LMK04828

 

Expirement :

  • Configuring DAC Software GUI to exercise Serial Data rate of 12.5Gbps on single Lane.
  • I am supplying 156.25MHz of External Reference Clock on SMA connector to LMK04828.
  • I am observing FPGA Clock of 78.25MHz across Capacitors C67/68 and DAC Clock of 156.25MHz across Capacitors C340/341 when probed on EVM.
  • The Expected Clock frequencies here is 312.5MHz and 625MHz respectively as shown in GUI

Please find enclosure for Screenshots pointing to errors observedTI CASE File.docx

  • 0
    TI__Guru* 78194 points
    Syed,

    With external clock mode, the LMK04828 on board is operating in clock distribution mode and buffers the input clock to the output dividers. In this mode, if you need to output 625MHz, you will need to provide 625MHz clock to the SMA input connector.

    You second method uses the LMK04828 in clock synthesizer mode, which generates the highest clock frequency needed in the setup by default.
    -Kang
  • 0 in reply to Kang Hsia
    Prodigy 65 points
    Thanks Kang, On Provding 625MHz Clocks to SMA input connector I am able to observe 625MHz DAC clock and also find 312.5MHz of FPGA Clock.

    After Programming FPGA evaluation platform I am running following steps on DAC GUI software :

    DAC3XJ8X GUI v1.1
    Stp-1 - Choose Clock Mode - External Clock
    Stp-2 - Choose DAC Configuration :
    Dev-DAC39J84
    DAC data i/p rate : 156.25MSPS
    Number of SERDES Lanes : 1
    Interpolation : 4

    Stp-3 - Stats!
    DAC output rate : 625MSPS
    FPGA Clock : 312.5MHz
    JESD204B Mode (LMFS) : 1481
    SERDES Linerate : 12500Mbps

    Stp 4 - Program LMK04828 and DAC39J84X and Also Reset DAC and JESD Core


    In ALARM and ERRORS I find DAC PLL out of Lock and SERDES PLL 1 out of Lock Flagging-ON

    Is this expected for External Clocking Mode?

    Only SERDES PLL 0 Out of Lock is asserted, Does this mean than SERDES PLL are Locked correctly ?
  • 0 in reply to Kang Hsia
    Prodigy 65 points
    Thanks Kang, On Provding 625MHz Clocks to SMA input connector I am able to observe 625MHz DAC clock and also find 312.5MHz of FPGA Clock.

    After Programming FPGA evaluation platform I am running following steps on DAC GUI software :

    DAC3XJ8X GUI v1.1
    Stp-1 - Choose Clock Mode - External Clock
    Stp-2 - Choose DAC Configuration :
    Dev-DAC39J84
    DAC data i/p rate : 156.25MSPS
    Number of SERDES Lanes : 1
    Interpolation : 4

    Stp-3 - Stats!
    DAC output rate : 625MSPS
    FPGA Clock : 312.5MHz
    JESD204B Mode (LMFS) : 1481
    SERDES Linerate : 12500Mbps

    Stp 4 - Program LMK04828 and DAC39J84X and Also Reset DAC and JESD Core


    In ALARM and ERRORS I find DAC PLL out of Lock and SERDES PLL 1 out of Lock Flagging-ON

    Is this expected for External Clocking Mode?

    Only SERDES PLL 0 Out of Lock is asserted, Does this mean than SERDES PLL are Locked correctly ?
  • 0 in reply to Syed Shafi
    TI__Guru* 78194 points
    Syed,

    Since only one lane is being used, the SERDES core #0 (with RX0, RX1, RX2, and RX#) is enabled, hence SERDES PLL #0 is locked. SERDES core #1 has RX4, RX5, RX6, and RX7, and is not being used in single lane mode.

    The DAC GUI setting by default does not program the on-chip PLL, hence DAC PLL lock alarm will be triggered.

    -Kang