• State TI Thinks Resolved
  • Locked Locked
  • Replies 4 replies
  • Answers 2 answers
  • Subscribers 46 subscribers
  • Views 1022 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DAC39J84 Unable to produce Analog output for Serial Data rate of 12.5Gbps

Syed Shafi
Prodigy 65 points
Other Parts Discussed in Thread: DAC39J84

I am trying to observe Square wave at analog outputs on DAC Channel OUT A ,  However JESD TX (FPGA) and JESD RX (TI DAC) are Synchronized still DAC unable to recover the digitzed data packets for Square wave.

LMFS -1481

I have verified the Serial Inputs to DAC Card at C197/198 of EVM to find 12.5Gbps of Serial data correctly. However DAC still unable to reproduce analog outputs for the same.

Please find the attached document for configuration settings done in GUI TI DAC Case.docx

Fullscreen test_jesd_148.txt Download 
LMK04828 
0x00 0x00
0x02 0x00
0x100 0x02
0x101 0x55
0x103 0x00
0x104 0x20
0x105 0x00
0x106 0xF0
0x107 0x11
0x108 0x61
0x109 0x55
0x10B 0x01
0x10C 0x20
0x10D 0x00
0x10E 0xF0
0x10F 0x76
0x110 0x08
0x111 0x55
0x113 0x00
0x114 0x00
0x115 0x00
0x116 0xF9
0x117 0x00
0x118 0x18
0x119 0x55
0x11B 0x00
0x11C 0x20
0x11D 0x00
0x11E 0xF9
0x11F 0x00
0x120 0x10
0x121 0x55
0x123 0x00
0x124 0x00
0x125 0x00
0x126 0xF9
0x127 0x11
0x128 0x08
0x129 0x55
0x12B 0x00
0x12C 0x00
0x12D 0x00
0x12E 0xF9
0x12F 0x00
0x130 0x08
0x131 0x55
0x133 0x00
0x134 0x20
0x135 0x00
0x136 0xF9
0x137 0x01
0x138 0x40
0x139 0x02
0x13A 0x00
0x13B 0xA0
0x13C 0x00
0x13D 0x08
0x13E 0x03
0x13F 0x00
0x140 0x00
0x141 0x00
0x142 0x00
0x143 0x12
0x144 0xFF
0x145 0x00
0x146 0x10
0x147 0x12
0x148 0x02
0x149 0x42
0x14A 0x02
0x14B 0x16
0x14C 0x00
0x14D 0x00
0x14E 0xC0
0x14F 0x7F
0x150 0x03
0x151 0x02
0x152 0x00
0x153 0x00
0x154 0x78
0x155 0x00
0x156 0x78
0x157 0x00
0x158 0x96
0x159 0x00
0x15A 0x78
0x15B 0xF4
0x15C 0x20
0x15D 0x00
0x15E 0x00
0x15F 0x0B
0x160 0x00
0x161 0x01
0x162 0x44
0x163 0x00
0x164 0x00
0x165 0x0C
0x166 0x00
0x167 0x00
0x168 0x0C
0x169 0x5B
0x16A 0x20
0x16B 0x00
0x16C 0x00
0x16D 0x00
0x16E 0x13
0x17C 0x15
0x17D 0x0F
DAC_RESET 
0x00 0x1
DAC3XJ8X 
0x00 0x0418
0x01 0x0003
0x02 0x2002
0x03 0xA301
0x04 0x00FF
0x05 0xFFFF
0x06 0xFFFF
0x07 0x3400
0x08 0x0000
0x09 0x0000
0x0A 0x0000
0x0B 0x0000
0x0C 0x0400
0x0D 0x0400
0x0E 0x0400
0x0F 0x0400
0x10 0x0000
0x11 0x0000
0x12 0x0000
0x13 0x0000
0x14 0x0000
0x15 0x0000
0x16 0x0000
0x17 0x0000
0x18 0x0000
0x19 0x0000
0x1A 0x0020
0x1B 0x0000
0x1E 0x1111
0x1F 0x1140
0x20 0x0000
0x22 0x1B1B
0x23 0xFFFE
0x24 0x0010
0x25 0x0000
0x26 0x0000
0x2D 0x0000
0x2E 0xFFFF
0x2F 0x0004
0x30 0x0000
0x31 0x0100
0x32 0x0000
0x33 0x0000
0x34 0x0000
0x3B 0x1800
0x3C 0x8220
0x3D 0x0088
0x3E 0x0808
0x3F 0x0000
0x46 0x0044
0x47 0x190A
0x48 0x31C3
0x49 0x0000
0x4A 0x0101
0x4B 0x0003
0x4C 0x0900
0x4D 0x0301
0x4E 0x0F0F
0x4F 0x1CC1
0x50 0x0000
0x51 0x00FF
0x52 0x00FF
0x53 0x0000
0x54 0x00FF
0x55 0x00FF
0x56 0x0000
0x57 0x00FF
0x58 0x00FF
0x59 0x0000
0x5A 0x00FF
0x5B 0x00FF
0x5C 0x1111
0x5E 0x0000
0x5F 0x0123
0x60 0x4567
0x61 0x000F
0x64 0x0003
0x65 0xFC0F
0x66 0xFF0E
0x67 0x0000
0x68 0x9307
0x69 0x9C0F
0x6A 0xBD05
0x6B 0xFF00
0x6C 0x0007
0x6D 0x00E0
0x6E 0x0000
0x6F 0x0000
0x70 0x0000
0x71 0x0000
0x72 0x0000
0x73 0x0000
0x74 0x0000
0x75 0x0000
0x76 0x0000
0x77 0x0000
0x78 0x0000
0x79 0x0000
0x7A 0x0000
0x7B 0x0000
0x7C 0x0000
0x7D 0x0000

  • 0
    TI__Guru* 78214 points

    Syed,

    One quick note is that you should check your FPGA to ensure that it supports 12.5Gbps of SERDES transmitter rate. The DAC39j84 and DAC39J84 EVM have been verified against both Altera and Xilinx platform to support up to 12.5Gbps of transmission rate. Some of the issues that may be causing the problem is your FPGA may not have sufficient swing to compensate for the PCB and connector loss. You may also need to check the PLL/DLL setting on your FPGA to make sure the SERDES block does not have too much jitter on the transmitter side.

    -Kang

  • 0 in reply to Kang Hsia
    Prodigy 65 points

    Hi Kang,

    For data integrity : I am probing differential ends on DAC39J84 EVM on Cap 197 and 196 RX0_P_N near chip.I find correct data been received here @ 12.5Gbps

    For Clocks, I am driving the reference clock to my FPGA SERDES using DAC EVM board from GTX_CLKP and GTX_CLKN.

    All the Clock alignments are properly getting locked on my FPGA.

    Unexpected GUI behavior:

    For -ve testing , GUI doesn't report any ALARM / errors on JESD Link Layer even if i give any random frequencies to DAC Source External Source . I am unable to understand this behavior.

    My Serial Data link rate breaks and Oscilloscopes decodes invalid characters, but DAC39J84 GUI doesn't report any errors in this case

    Regards,

    Shafi

  • 0 in reply to Syed Shafi
    Prodigy 65 points

    Hi Kang,

    I have attached the Screenshots for Eye Monitor and Jitter analysis & voltage levels observed on Serial inputs lanes of TI DAC EVM

    All the voltage levels and jitter are under control limits.

    I am using Single serial lane here , hence captured all the screenshots by probing differential inputs across series capacitors for RX0 P and N near DAC39J84 Chip.

    Serial data was monitored using 23GHz Tektronix Scope.

    Eye Monitor Analysis :

    I am sending constant A5A5 patterns @ 12.5Gbps with LMF setting of 148 and K=5, The Oscilloscope is successfully able to decode all the data packets on the serial  inputs  of Oscilloscope. Please find the attached decoded data log showing correct decoding of data packets.

    DAC 39J84 EVM decoding is taking more time at our end, we have relied upon this DAC for our 12.5Gbps validation activities. It's been since 3 days we are unable to find any results in this regard. The DAC GUI is not guiding to correct outputs as -ve testing are also not flagging any errors.

    I would appreciate if you/any technical supp may help us out over a call for 15-30mins . This is effecting our Silicon tapeout this month.

    Regards,

    Shafi

    Fullscreen TI_DAC_input_A5A5_Log.txt Download 
    Index	Start Time	Type	Symbol	Character	Data (hex)	Data (binary)	Error/Warning
0	-5.37E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
1	-5.28E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
2	-5.20E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
3	-5.12E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
4	-5.04E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
5	-4.96E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
6	-4.88E-08	Control	11 0000 0111	K28.7+	--	--	
7	-4.80E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
8	-4.72E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
9	-4.64E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
10	-4.56E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
11	-4.48E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
12	-4.41E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
13	-4.32E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
14	-4.24E-08	Control	11 0000 1100	K28.3+	--	--	
15	-4.17E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
16	-4.08E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
17	-4.00E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
18	-3.92E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
19	-3.84E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
20	-3.76E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
21	-3.68E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
22	-3.60E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
23	-3.52E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
24	-3.44E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
25	-3.36E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
26	-3.28E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
27	-3.20E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
28	-3.12E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
29	-3.04E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
30	-2.96E-08	Control	00 1111 1000	K28.7-	--	--	
31	-2.88E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
32	-2.80E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
33	-2.72E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
34	-2.64E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
35	-2.56E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
36	-2.48E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
37	-2.40E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
38	-2.32E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
39	-2.24E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
40	-2.16E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
41	-2.08E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
42	-2.00E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
43	-1.92E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
44	-1.84E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
45	-1.76E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
46	-1.68E-08	Control	00 1111 1000	K28.7-	--	--	
47	-1.60E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
48	-1.52E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
49	-1.44E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
50	-1.36E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
51	-1.28E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
52	-1.20E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
53	-1.12E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
54	-1.04E-08	Control	00 1111 0011	K28.3-	--	--	
55	-9.66E-09	Data	10 1001 1010	D5.5	A5h	10100101b	
56	-8.84E-09	Data	10 1001 1010	D5.5	A5h	10100101b	
57	-8.04E-09	Data	10 1001 1010	D5.5	A5h	10100101b	
58	-7.24E-09	Data	10 1001 1010	D5.5	A5h	10100101b	
59	-6.44E-09	Data	10 1001 1010	D5.5	A5h	10100101b	
60	-5.64E-09	Data	10 1001 1010	D5.5	A5h	10100101b	
61	-4.85E-09	Data	10 1001 1010	D5.5	A5h	10100101b	
62	-4.05E-09	Data	10 1001 1010	D5.5	A5h	10100101b	
63	-3.25E-09	Data	10 1001 1010	D5.5	A5h	10100101b	
64	-2.44E-09	Data	10 1001 1010	D5.5	A5h	10100101b	
65	-1.64E-09	Data	10 1001 1010	D5.5	A5h	10100101b	
66	-8.43E-10	Data	10 1001 1010	D5.5	A5h	10100101b	
67	-4.44E-11	Data	10 1001 1010	D5.5	A5h	10100101b	
68	7.58E-10	Data	10 1001 1010	D5.5	A5h	10100101b	
69	1.56E-09	Data	10 1001 1010	D5.5	A5h	10100101b	
70	2.36E-09	Control	11 0000 0111	K28.7+	--	--	
71	3.15E-09	Data	10 1001 1010	D5.5	A5h	10100101b	
72	3.96E-09	Data	10 1001 1010	D5.5	A5h	10100101b	
73	4.76E-09	Data	10 1001 1010	D5.5	A5h	10100101b	
74	5.56E-09	Data	10 1001 1010	D5.5	A5h	10100101b	
75	6.35E-09	Data	10 1001 1010	D5.5	A5h	10100101b	
76	7.16E-09	Data	10 1001 1010	D5.5	A5h	10100101b	
77	7.95E-09	Data	10 1001 1010	D5.5	A5h	10100101b	
78	8.76E-09	Data	10 1001 1010	D5.5	A5h	10100101b	
79	9.56E-09	Data	10 1001 1010	D5.5	A5h	10100101b	
80	1.04E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
81	1.12E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
82	1.20E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
83	1.28E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
84	1.36E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
85	1.44E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
86	1.52E-08	Control	11 0000 0111	K28.7+	--	--	
87	1.60E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
88	1.68E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
89	1.76E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
90	1.84E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
91	1.92E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
92	2.00E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
93	2.08E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
94	2.16E-08	Control	11 0000 1100	K28.3+	--	--	
95	2.23E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
96	2.32E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
97	2.40E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
98	2.48E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
99	2.56E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
100	2.64E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
101	2.72E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
102	2.80E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
103	2.88E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
104	2.96E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
105	3.04E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
106	3.12E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
107	3.20E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
108	3.28E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
109	3.36E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
110	3.44E-08	Control	00 1111 1000	K28.7-	--	--	
111	3.52E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
112	3.60E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
113	3.68E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
114	3.76E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
115	3.84E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
116	3.92E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
117	4.00E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
118	4.08E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
119	4.16E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
120	4.24E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
121	4.32E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
122	4.40E-08	Data	10 1001 1010	D5.5	A5h	10100101b	
123	4.48E-08	Data	10 1001 1010	D5.5	A5h	10100101b

  • 0 in reply to Syed Shafi
    TI__Guru* 78214 points

    Hi Shafi,

    I suggest we try a couple of things:

    1. on the SERDES level, the DAC39j84 has PRBS7, 23, and 31 receiver test capabilities. Please try the following method described in the datasheet to ensure the pattern is received correctly

    2. I would also suggest slow down the SERDES interface rate to see until the link start working.

    3. Once the SERDES level checks out, let's move to JESD204B logic test. Please see attached to check the JESD204B IP on your side against our side:

    5001.7.3.1.2.5 JESD204B Pattern Test.docx

    4. I noticed that in your previous discussion that some of the GUI parameters are not set correctly. For instance, on the termination selection for the SERDES, the setting is set to invalid mode. It should be set to AC coupled mode for proper receiver setting. I would check to see if somehow the programming got reset or something.

    I will private message you regarding additional support.

    -Kang