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ADS1271: F_SCLK faster than F_CLK

Sergio L.
Prodigy 10 points
Other Parts Discussed in Thread: ADS1271

Hello,

 We're porting a design from a previous ADS to ADS1271. The system uses the SPI interface to read data with F_SCLK = 15 Mhz, but the conversion clock is set to F_CLK = 300 Khz aprox. This violates the technical specification, which states that  fSCLK must be lower or equal than fCLK.

We use only the first 16 most significant bits, and discard the remaining 8.

I want to know if this will work anyway, so we don't need to change the design. We don't care if some noise appears on the lower 8 bits. I DO care if the communication is scrambled because of the "invalid" SCLK frequency.

Thank you,

 Best regards, Sergio L.

 

 

  • TI__Guru* 97415 points

    Sergio,

    I've looked through the design, but I haven't been able to come to a specific answer to your question.

    It looks like clocking out data may not be a problem, the output register is based on the SCLK advancing the shift register. While in general, this might work, I certainly wouldn't recommend it.

    Often the SCLK is used to clock something in, but is gated by the master clock. I do know that certain resets are gated by the master clock and there is a possibility that the timing of an internal reset as used by the digital filter may be changed. Also, I'm also not aware of what other possible issues might come up by speeding up the SCLK. It's likely that the problems encountered in overclocking SCLK are not as simple as noise on the lower LSB and more likely something that will disrupt operation.

    In short, I'm sure there is a reason that the SCLK frequency is specified to be a maximum of the CLK frequency, but I wasn't able to find it and the digital designer is no longer available for questions.

    Sorry I couldn't be any more help.

    Joseph Wu