ads1298 timing requirements

Noel Teku

Other Parts Discussed in Thread: ADS1298

Hello,

On page 17 of the ads1298 datasheet, there is a table that specifies various timing requirements that must be met. However, only one, 'tclk', has a minimum and maximum value. In the case of 'tsclk', for example, that only has a minimum. Does this mean I need to delay for only that minimum specified amount of time when communicating with the ADS1298?

Thanks,

Noel Teku

over 9 years ago

0 Brian Pisani over 9 years ago

TI__Mastermind 38745 points

Hey Noel,

Most microcontrollers with integrated SPI modules will allow you to configure frequency of the SCLK. In the case of the ADS1298, the maximum SPI clock frequency that is allowable is 1/tsclk. Anything above that cannot be guaranteed to work properly.

Brian

0 Noel Teku over 9 years ago in reply to Brian Pisani

Intellectual 430 points

Hey Brian,

Thanks for responding so quickly! So I'm planning on using my PIC's clock for this SPI interface. Tsclk only has a minimum limit of 50 ns according to the datasheet. Does this imply that because tsclk does not have a maximum limit, I can set it to an arbitrary value as long as it is greater than 50 ns?

Thanks,
Noel Teku

0 Brian Pisani over 9 years ago in reply to Noel Teku

TI__Mastermind 38745 points

Noel,

From an electrical point of view, yes. From a logic execution point of view, SCLK frequency cannot be arbitrarily low since you will have to run fast enough to obtain all the data between DRDY signals. Make sense?

Brian

0 Noel Teku over 9 years ago in reply to Brian Pisani

Intellectual 430 points

Yes it does! Thanks Brian!

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ads1298 timing requirements