ADS5263 Driving Circuit

Hi,

the ADS5263 is supported by our Medical Group so I will transfer this posting to that forum.

Regards,

Richard P.

Hello Boniello,

How are you?

Thank you for using our ADS5263 device.

Please take a look at TI ADS5263 User's Guide as the following link:

www.ti.com/.../technicaldocuments

On its page 5 and page 6 (also you can test on ADS5263 EVM's CH_IN3A SMA at connector J30)

the ADS5263 User's Guide shows you one example of how using differential Op Amp

which is THS770006 fully-differential amplifier to drive the ADC.

Notice: here is the spec of this THS770006 op-amp

1) its Gain is fixed and set to be 6dB (gain = 2)

    does it fit your needs?

2) its signal frequency bandwidth can be up to 2.4GHz BW range.

    so when you are using it, you may need to setup a bandpass or lowpass filter

    between THS770006 op-amp and ADS5263 ADC.

    On ADS5263 EVM, we keep (reserve) many spaces for you to add more components

    for creating the bandpass filter range and spec for your need.

    (Please take a look at ADS5263 User's Guide Page5 and Page6

     and THS770006 Data Sheet Page25 to Page27.

     You can observe more examples of how to use them.

Thank you very much.

Best regards,

Chen

Hi Chen,
first of all thanks for the prompt answer.
1)I really wish a gain of 1 in voltage, because the signal to be digitalized varies betweenn -2V and +2V, so I was hoping to use the 4Vpp full input range of the ADC. If I would use a gain of 2 I would be out of the ADC specs. Could you perhaps suggest me another op amp? Or I can just use 50 Ohms in series on the inputs to get gain=1?
2)Are you sure a need a Bandpass filter? My input Bandwidth on the ADC would be circa 1.5 MHz, and then I need to sample that at 100MSPS
I was thinking more about a stand RC Filter between the op amp and the ADC.
3) Technical question: what are the advantages/disadvantages of using transformators on the input or alternatively fully differential op amps?
I mean, I tought the differential op amp was perfect because I can use it also as a level shifter to shift the signal from -2V/+2V (VCM=0) to a positive VCM, the one from the ADC.

Hello Giulio,

Thank you for more detail information for using amplifier for ADS5263 input signal source.
Since THS770006 amplifier gain=2 is fixed, it does not really fit your need.
Please refer to THS413x (for example THS4131 fully differential amplifier).
Please look at its Data Sheet.
1) It is also fully differential op-amp and can work at gain=1.
2) Its bandwidth is not too high (BW -3dB at 150MHz)
3) it has low noise 1.3nV/VHz at 10kHz
4) Please notice that the output signals are inverted to the input signals when using
fully differential amplifier.
5) Of course please add a low pass filter differentially between op-amp (such as THS4131) output pins and ADC ADS5263 input pins. This LPF can fit your input bandwidth within your input signal BW.

Thanks for using ADS5263 device.

Best regards,
Chen

Hi Chen,
thanks again.
I have another question: the ADS5263 can sample is input up to 100MSPS, and then deliver the bits in a much higher frequency due to the serial LVDS, or there is some limit for the sampling clock?
I mean, I need to sample at 100 MHz, but this means also to me that my output data rate would be higher then 100 MHz on the output channels. Correct?
Thanks in advance
Giulio

Hello Giulio,

How are you?
Thanks for using ADS5263 device.

The 100MHz Clock is coming from the outside of the ADS5263 device.
(such as using external clock or OSC built on the board.)
As you can see more detail description from the ADS5263 Data Sheet Page 16.
Inside the device, ADS5263 itself will generate 8 * 100MHz = 800MHz freq (called BIT Clock).
This BIT clock is the clock to deliver the data bit (serial data) into FPGA to receive the AFE5808's Output serial Data.
And its Output Data Rate (the highest rate) is = 16 * 100MHz = 1600 MHz Data Rate for FPGA to capture.
That is the reason of why the FPGA needs to be fast enough to capture high speed data from the outside (for example, TSW1400 Capture Board can capture high speed data from ADS5263.)

Thank you very much again.

Best regards,
Chen

Hey Chen,

my plan is to use the the 2xWire 16 bits serialization, as I understood this would mean I would have a bit clock of x4 the Sampling Clock.

What about the Voltage level of the LVDS Interface? If i get it right, the LVDS Outputs are supplied by 1.8V, and they have a VCM (typical) of 1.2V.

Would it work if the output lanes of the ADS5263 are connected with FPGA pins supplied with 2.5V insted of 1.8V?

Hello Giulio,

How are you?

Here is the LVDS output spec from ADS5263 data sheet:

Please take a look:

Very similar to what you mentioned.

If you have a copy of the TSW1400 schematics, then please take a look at its page 3 and page 12.

You can see how ADS5263 EVM digital output pins are connected to TSW1400 capture board.

Here are some examples from TSW1400 schematics:

(You can compare them to the ADS5263 EVM schematics from the User's Guide).

Thanks and best regards,

Chen

Hi Chen,

I have some questions about the THS4131 Op Amp.

I´m planning to use the internal reference of the ADS5263 (1.5V) as VCM for the fully differential TSH4131 amplifier, powering it with 5V on the positive supply and GND on the negative.

From datasheet (Page 6) I see that the output swing when VCC=5V is not guaranteed up to the values that I need: my output signals would vary from 0.5V to 2.5V, but the minimum Vout is 1.2V ( but a typical of 0.9V).

1) Anyway, it I power it also with -5V on the negative supply, so that VCC=+/-5, the output voltage swing range would be okay for me if I understand correctly (+/-3.7V). Would this configuration bring problems? I mean, powering the OP Amp also with a negative voltage but using anyway a positive VCM? At the end, I would just use the negative supply to get the necessary output voltage swing, but I don´t need the OP Amp to really output any negative voltage.

2) If this configuration it´s not possible, could you please suggest me some other op amp to drive the ADS5263 which has the necessary output voltage swing (from 0.5V to 2.5 V) with 5V single supply?

Thanks in advance

Giulio

Hello Giulio,

How are you?

Thanks for your detail information of the input signal requests for ADS5263 device.

Yes, you are correct. Each analog input signal range (INP and INM) for ADS5263 is speced as:

Input Max voltage = 2.5V

Input Min voltage = 0.5V

Vcm = 1.5Vdc

When you are using THS4131 Opamp

(similar to using THS770006 Opamp, please refer to the ADS5263 User's Guide as well),

you need to use AC-Coupled method to separate the differences between Opamp common mode voltage

and ADS5263's common mode voltage.

If this is not possible to do, then you can choose to use +5V and -5V power supplies for THS4131 Opamp.

This can avoid the Input Min voltage (0.5V) getting clipped by Opamp (due to the Opamp's negative supply tied to GND).

Of course if you only can provide positive power supply to your EVM boards, then you can choose

rail-to-rail Opamp (such as THS452x, THS4541 devices).

Both can provide you Single-Supply Voltage (such as +5V and GND)

 and very low output voltage (such as 0.2V).

Please take a look at their data sheets and see if they can fit your needs.

Thank you very much of using our ADS5263 device.

Best regards,

Chen

Hey Chen,

for the prototype I plan to use only one input channel of the ADC.

What am I supposed to do with the Inputs and Outputs which I won´t use, should they be tied to Ground or just left floating?

Thanks

Best Regards

Giulio

Hello Giulio,

How are you?

If ADS5263 one channel is active but its input signal (analog) is floating,

then its output signal (digital) will be unknown and risky.

So it is not good to let the input be floating.

For example, please look at the following example:

This CH1 input SMA connecter J14.

Usually we connect this input SMA to the sine wave signal.

But if we don't do so, then we tie this SMA to GND.

Thank you for using ADS5263.

Best regards,

Chen

Hi Chen,

I was looking at the THS4131 to know how much current the VOCM pin needs the function properly. I couldn´t find the explicit  information on the datasheet, but I would speculate that the value I´m looking for is the input bias current. I mean this is definetly valid for the inputs, but also for the VOCM pin?

Best regards and thanks in advance

Giulio

Hello Giulio,

One engineer is using THS4131 as the amp to drive his AFE input.

I would ask him how much details about THS4131's VOCM input bias current requirement.

Thanks and best regards,

Chen

Hi Chen,
on Figure 1, page 14 of the ADS5263 Datasheet I see the Reset Timing Diagram, and the descripiton say that I need a HIGH-going Pulse on the RESET pin for the initialization. Anyway at page 7 and page 43 is clearly described the necessitiy of a LOW-going Pulse on the RESET pin for the Initialization. Which one is correct? Also, are the Reset Switching Characteristics on page 14 reliable?

Best regards and thanks in advance

Giulio

Hello Giulio,

How are you?

Last time when concerning about the current driving capability for THS4131 Vocm by using ADS5263.

ADS5263 can provide VCM output current capability at 3mA.

Although THS4131 datasheet does not mention about what is the current required for Vocm

however there are two examples are shown on the THS4131's datasheet.

One is using THS1050 Vcm to drive THS4131 Vocm is 10uA max.

Another one is using THS1206 REFOUT to drive THS4131 Vocm is 250uA max

Both have less than current driving capability than ADS5263.

So it could be working correctly while using THS4131 and ADS5263.

also another question for setting RESET signal.

Yes, you are correct.

Page7 RESETZ pin definition is correct and Page14 RESET plot is not correct.

Please look at the following correction.

Page#7:

Page#14:

I will mention this issue to our design engineer group.

Thank you very much.

Best regards,

Chen

  

Hi Chen,

thanks for your quick answers. Anyway I have 2 questions more :-) :

1) On page 12 of the ADS5263 Datasheet I see the minimum (6.8 ns), typical (8.8ns) and maximum (10.8 ns) values of the Clock Propagation Delay (Tpdi) for 2 wire, 8x Serialization mode. On the next page this values are referred only to the Tdelay Parameter. This means that for correct calculation should I add to the upper values the Ts/4 or not?

2) Is the ADC Latency of 16 Clock Cycles indipendent from Sampling Frequency, Output mode and other settings?

Thanks in advance and best regards

Giulio

Hi Giulio,

For your 1) question:

Since you may use 2 wire, 8x serialization mode for ADS5263 device.

Then the propagation delay Tpdi is listed on the ADS5263 data sheet page 12:

Tpdi = (ts/4) + tdelay

and tdelay (min=6.8ns, typical=8.8ns, max=10.8ns)

Assume we are running Clock fs at 50MHz, then ts=1/50Mhz=20ns

and if the tdelay is = typical 8.8ns, then Tpdi = (ts/4) + tdelay = (20/4) + 8.8 = 13.8ns

2) For the ADC Latency:

16 Clock cycle will depend on the your clock frequency speed.

For example, if you are running 50MHz clock,

then ADC clock cycle is still the same = 16

but its timing is 16 * 1/50MHz = 16 * 20ns = 320ns.

Hopefully these explanations are more clear for you.

Thanks and best regards,

Chen