This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
I am making use of the ADS6144 in a custom board with spartan 3a dsp 3400. I have set it for LVDS configuration with the following register settings:
/*
*Performing write to 0x00
*/
Cmd=0x0010;//first reset the internal registers
Cmd=0x0100;
/*
*Performing write to 0x04
*/
Not needed
/*
*Performing write to 0x09
*/
Cmd= 0x4C00;
/*
*Performing write to 0x0A
*/
Cmd= 0x5400;
/*
*Performing write to 0x0b
*/
Not done
/*
*Performing write to 0x0c
*/
Not needed
/*
*Performing write to 0x0E
*/
Cmd= 0x7000;
/*
*Performing write to 0x0F
*/
Not needed
This works for test patterns.....but when I give an adc input i do not get the output. I make the relevant change for register 0x0A to change from test pattern mode to adc output mode(normal operation)..... Could anyone please tell me what the mistake could be????
r
Hi,
To make LVDS output through serial interface/register, the reset pin canot connected to 3.3v, it can be floating (it has 100 kohm pull-down internally). Please reference our EVM schematic for how to set reset pin. Before send any control code please send reset code first, you did this right. After sending reset code, then you can try power down code to see if the device and SPI works, by doing this you can send 00(address) 001(data) and check source current change (should be lower than normal current), then send reset code again to bring the part back to the normal. If power down works then you can set 00 100 for LVDS DDR output, then send 00 400 for straight binary outpu data format. Before you do this please check the DC voltage on the device, for example Vcm.
Please try this and it should work (the code provided here I the one I used on EVM board).
Regards,
Qing
Hi,
Yes I have followed your instructions and tried out the settings you have provided. The power down mode works. But like I said earlier the test patterns work on my board,
I am able to generate the all zeros,all ones, toggle pattern and ramp pattern. So I am sure that both the spi and device work. The reset pin was connected as you described. Vcm
is proper. I am getting data from adc buffer, but it is not when reconstructed matching with my input, it made me doubt my device configuration..... but now I have followed your
settings and am getting the same thing.
Could you please tell me your input signal setup(frequency of signal,signal Vpp,sampling rate being used) and how many samples it took you to reconstruct your waveform?
regards
Lakshmi
Hi,
When you say you don't get data out at input signal adding to the input pin, does this mean you don't get the correct wave form or you don't get output (just noise)? If you don't get correct wave form, it needs set correct data format and output mode (LVDS/CMOS) through rigister. For input signal we used is a sine wave in general, frequency 1 Mhz for test is good, 2Vpp differential is the max, we use transformer coulping signal from source to ADC, use BPF at input path and clock path, clock condition should be in spec (please see EVM user guide and data sheet spec table for details). As an example, sample size 8k is good, at 105MHz or 80Mhz clock with 1Mhz analog input, you should be able to see a good digital sine wave at ADC output. Make sure you are at normal operation mode (not test mode) if you want test input signal.
Regards,
Qing
Hi,
Here are some more ponits based on the e-mail you mentioned. It sounds you have got the data from ADC into the receiver, but you can’t reconstruct the sine wave from the data collected. It sounds to me you should check following things, how you converter DDR data format into normal data in FPGA side? Chip scope sampling rate, how it relative to data capture clock and data? If you are using the output clock of ADC to capture the data please see the figure 1 and 2 in the data sheet for the timing and DDR data format, note that the data is capture at both edges of the output clock if you are using the output clock. After convert DDR data into normal data you should see a reasonable digital sine wave at a low frequency input and high sampling rate. If you want to get a unwrap sine wave from the raw data that is a different thing from EVM setup.
Regards,
Qing