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ADS6144: ADS61xx output format control

Mark McLean
Prodigy 30 points
Part Number: ADS6144


Hi,

I am designing a board where an ADS6144 will be connected to a Cyclone 10GX FPGA.  This FPGA (like many newer devices) does not have many 3V tolerant pins.  I would like to use the LVDS interface of the ADS6144 and connect it to the 1.8V I/O domain of the FPGA.  I would also like to configure the ADC using its serial port rather than pin-strapping, because I want to use the test data features of the ADC.  This should be fine, but I worry that a one bit programming error in the selection of the output mode could cause the output to enter CMOS mode and destroy the input buffers of the FPGA.  Is there anyway to force the part into LVDS mode while still using serial configuration?

Cheers, Mark

  • 0
    TI__Mastermind 23880 points

    Hi Mark,

    It is not possible to set LVDS mode as a default mode for this device. You can program the output buffers to be disabled according to the datasheet (Table 4/5) while setting the output mode. Or (I imagine) you can also disable the input buffers on your FPGA while verifying that the ADC register programming is consistent.

    Because the datasheet does not show what the default values are, next week I will run some tests on what the default register values, operating mode, and output levels are after a reset and post findings here.

    Regards