SPI: CLK connections to ADS1298ECGFEPDK

Noel Teku

Other Parts Discussed in Thread: ADS1298

Hello,

I want to verify one pin connection I'm making between my PIC and the ADS1298ECGFEPDK. I was about to connect the CLK (SPI) pin of my PIC to the pin labeled SCLK on J3 of the ADS1298ECGFEPDK, but I'm not sure if I should connect it there or to the pin labeled EXT_CLK also on J3. Also, is CLKSEL accessible through J3 as well, or is it represented by JP23 ? I've delegated a pin on my PIC to control CLKSEL, but if it is only accessed through JP23, how I would be able to connect my pin to it?

Thanks,

Noel Teku

over 9 years ago

0 Otavio Augusto Gomes over 9 years ago

Intellectual 940 points

Hey Noel,

EXT_CLK is the external clock for ADS1298 operation (data sampling and internal operations) and not for SPI data transfer. The ADS1298 demonstration Kit has an external 2.048 Mhz Crystal connected to EXT_CLK that provides external clock for ADS1298. In order to clock the SPI, just use the SCLK pin. If you want change CLKSEL, for any reason, just remove JP23 and connect you microcontroller I/O pin instead. Remember that CLKSEL switches the ADS1298 clock source between internal and external, and has no relation to SPI clock. The SBAU171D User Guide may help you to understanding the right ADS1298 pin functions.

0 Noel Teku over 9 years ago in reply to Otavio Augusto Gomes

Intellectual 430 points

Hi Otavio,

Thanks for the quick response! So does that mean that the clock for SPI is not considered as an external clock? The only reason I gave a pin for CLKSEL was because I thought I needed it to tell the ADS1298 to use the SCLK instead of its internal clock?

Thanks,
Noel Teku

0 Otavio Augusto Gomes over 9 years ago in reply to Noel Teku

Intellectual 940 points

Hey Noel,

The ADS1298 has two types of clock signals. The clock for operation of the converter (signal sampling and internal operations) that must be 2.048 Mhz. In this case, the ADS1298 may either uses an internal clock generator (available internally on the chip) or use an external clock source close at 2.048 Mhz such as a quartz crystal or from a microcontroller. CLKSEL signal switches between internal and external, and has no relation to SPI clock. SPI clock (SCLK pin) is used for SPI communication only, You do not need change CLKSEL to use SCLK pin. CLKSEL has no relation to SPI clock. SPI clock rate must be chosen according to the number of channels used (1 to 8 in ADS1298) and other settings.

0 Brian Pisani over 9 years ago in reply to Otavio Augusto Gomes

TI__Mastermind 38745 points

Looks like Octavio has things under control here :-)

0 Noel Teku over 9 years ago in reply to Otavio Augusto Gomes

Intellectual 430 points

Hi Otavio,

Thank you so much! This clarifies a lot! Do you know where in the datasheet they discuss choosing the clock rate against the number of channels?

Thanks,
Noel Teku

0 Noel Teku over 9 years ago in reply to Brian Pisani

Intellectual 430 points

Yup! Thanks Brian!

0 Otavio Augusto Gomes over 9 years ago in reply to Noel Teku

Intellectual 940 points

Sure Noel,

Take a look in the page 59 of the SBAS459K.

You find it

0 Noel Teku over 9 years ago in reply to Otavio Augusto Gomes

Intellectual 430 points

Hi Otavio,

Thanks so much! I have three question regarding this equation:

- Because the ADS1298 has 24-bit ADC's, does that mean that Nbits will always be 24?
- I just want to ask this question to be sure. I'm planning on only using channel 3, so does that mean that I would set Nchannels = 1?
- How is tDR determined? I know that's referring to the data rate, and I'm planning on using 500 Hz as my sampling rate, but I can't seem to find where the datasheet explains how to determine what tDR is?

Thanks again,
Noel Teku

0 Brian Pisani over 9 years ago in reply to Noel Teku

TI__Mastermind 38745 points

Noel,

-Yes
-No you'll have to shift out 3 channels, but the first two channels will be 0x00s.
-tDR = 1/fDR. For fDR = 500 SPS, tDR = 2 ms.

Brian

0 Noel Teku over 9 years ago in reply to Brian Pisani

Intellectual 430 points

Hi Brian,

Thanks so much! So does that mean that Nchannels= 8 always? Also, I just want to make sure I understand. I've configured each channel's register so that only Channel 3 is enabled. So does that mean that when the data is coming into my PIC, in order to use channel 3, I'll still have to parse through a certain length of data( as you've said, skipping the first two channels) in order to access channel 3's data?

Thanks,
Noel Teku

0 Otavio Augusto Gomes over 9 years ago in reply to Noel Teku

Intellectual 940 points

Noel,

No, Nchannels (in that equation) will be the last enabled channel. In this case (3). The data frame consists of 24 status bits + 24 bits from channel one + 24 bits from channel two + 24 bits from channel three. Your microcontroller application must shift out the status bits + 3 channels. So after, the application can discard the status bits and data from channel one and channel two.

0 muhammad ather over 9 years ago in reply to Otavio Augusto Gomes

Intellectual 310 points

hi Otavio,
Sorry I am Interrupting your discusssion. I am not getting minimum fsclk = 110 KHz using 500 SPS, eight channels, 24 bit resolution and 2.048MHz clock.
Can you please explain how this 110KHz is derived using the above relation

regards

0 Brian Pisani over 9 years ago in reply to muhammad ather

TI__Mastermind 38745 points

Hello Muhammad,

t_dr = 1/500 SPS = 2 ms
t_clk = 1/2.048 MHz = 488 ns
N_bits = 24
N_channels = 8

t_SCLK = (2e-3s- 4*488e-9s)/(24bits*8channels + 24bits) = 9.25 us
f_SCLK - 1/t_SCLK = 110 kHz

Regards,
Brian

0 muhammad ather over 9 years ago in reply to Brian Pisani

Intellectual 310 points

Thanks Brian

Data converters

Data converters forum

SPI: CLK connections to ADS1298ECGFEPDK