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DAC37J84EVM possible bug

Other Parts Discussed in Thread: DAC37J84

Hello,

This is a question about the DAC37J84 v1.1 GUI, screen DAC3XjX Controls, Dig Block 1, ABQMC EN.   

DAC channel A and B are outputting 100 MHz sine waves, 60 deg apart at sample rate = 983.04 MHz.     I set Phase AB = 0, Gain A = 512, Gain B = 512.  When I click AB QMC EN the sine waves phase jumps about 100 degrees.  When I click QB QMC EN off the phase goes back to normal.   This does not seem correct. what do you think is happening?   I checked register config 16 and it seems that qmc_phaseab is zero. 

Thanks very much,

John Reyland

  • Hi Jon,

    Are you using TSW14J56 RevD to generate pattern for DAC evm? I tried your setup with DAC EVM and TSW14J56 Rev D pattern generator. When I generate REAL signal on TSW14J56 and send it to DACs channel A and Channel B. The two channels should be 180 out of phase with QMC enabled or disabled. Please see the screen shots I took from the Oscope as you can see when I enable QMC with your settings (Phase AB = 0, Gain A = 512, Gain B = 512). The only thing that change is amplitude of signal not the phase which is as expected and there 180 degree phase between the two.

    And when I generate complex signal, the two outputs are off by 90 degrees as expected and again enabling QMC with your settings does not change phase it only changes amplitude as shown in figures below.

    Also, I am not sure why your are seeing 60 degree phase difference between the two outputs. Are both the SMA cables that you use to connect the DAC outputs to Oscope same length?

    Regards,

    Neeraj Gill

  • HI Jon,

    Also want to mention please make sure config30 Addr 0x1E BIT 12 and BIT 4 are set to '1'. and also in config31 Addr 0x1F bit 1 is toggle FOR SIF SYNC signal.

    Regards,

    Neeraj Gill

  • Hi Neeraj, We got around the problem of the DAC output channel phase jumping when the corresponding QMC_ is enabled. We are driving the 37J84 EVM with sine waves on 8 lanes of JESD from a Xilinx Virtex 7 EVM. When we checked the AB QMC EN, and CD QMC EN in the TI GUI prior to starting up the Virtex program, the problem went away and we can correctly adjust the DAC output scaling in the GUI. We get the phase jumps when we change the QMC EN at the same time the JESD lanes are running full speed. I have no idea why. Thanks for your help! John Reyland