Hi

Changhoon,

What ADC is this question in reference too?

Regards,

Jim

Jim,
That is "ADS4249EVM ".
Regards,
Changhoon

ChangHoon,

For CHA, if R25, R26, and C65 are installed, this is a HPF that may be effecting your high frequency input signal. These are usually removed when testing high frequency analog inputs.

Regards,

Jim 

Jim,
I am so sorry for making you confuse.

Thanks for your reply, but I still can not understand completely.
When I input analog signal which has 1.5 ns width and 250 MHz sampling frequency into the ADS4249EVM.
Then, how many sampled points can I get from the input signal?
I think that I can not get any digital value from the signal because ADC sampling resolution is 4 ns (Sampling frequency = 250 MHz), is it right?
However, I can get 4 digital value when I test the ADS4249EVM. How can I get 4 digital value?
Is there some problems?

Thanks and Regards,
Changhoon

ChangHoon,

Is you input a sinewave or a pulse? If it is a sinewave, and you keep it under 600MHz, you will be able to get valid samples over time. This is called under-sampling. If you are sending a pulse, you will not get valid samples. In either case, it appears your signal is at 666.666MHz, which is higher than the maximum input bandwidth of this part (600MHz with 1V p-p clock). You need to look at a faster sampling device. If you need recommendation, let me know how fast you can sample at, how many channels you need, and any power requirements.

Regards,

Jim

Changhoon,

Can you please send us a screen shot of the captured signal? The 1.5ns pulse corresponds to about 666MHz fundamental with higher order harmonics, sampled at 250Msps, this will alias back to 166M which will fall at 250-166=84M.  You may be seeing this alias component.

Ken.

Jim and Ken,

I am sorry but, now I can not reply your requests.

However, I have a additional question. Currently, I want to modify the board for DC coupling.

If you know how I can do this modification, please send me documents about that.

Thanks,

Changhoon

ChangHoon,

The ibis models were just for the io pins and did not include the sample clock and analog pins and vcm.   But the datasheets had detailed schematic representations of the clock and analog inputs suitable for a spice or Tina simulation, so these were captured into Tina models.  Right out of the datasheets.   Thus there is no overlap between the Tina models and the ibis models.   Ibis is the digital io, Tina is the clock and analog inputs.   There would be no ‘output’ from the Tina models.  Inputs only.  The idea was to have something to let the driver and filter be modeled with an accurate representation of the ADC to finish the path, including the vcm termination after AC coupling and the sampling glitches from the clock back through the analog pins.  

Regards,

Jim

ChangHoon,

I would recommend to do the following on Channel A:

1. Replace C11 = 0.1uF with 0ohms

2. Remove T1, and short with 0ohms across pins 4 &3 and 6 & 1 of T1

3. Make R119, R123, R141 and R143 as DNI

4. Install with 0 ohms for R120, R129, R131 and R132

5. Replace the C13 and C66 with 0 ohm resistors.

6. Make R37 and R39 as 88.7 ohms

7. Make R42 and R19 as 73.2 ohms

8. Replace C51 with 0 ohms

 

The above board change should configure the THS4509 in single-ended to differential DC coupled input configuration with Gain = 3.48V/V

Regards,

Jim

ADS42XX_58C28EVM-SCH_C.pdf