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ADS1252 When the DOUT mode, CLK can use to stop?

cafain
Mastermind 6755 points
Other Parts Discussed in Thread: ADS1252

Hi,

ADS1252 Datasheet (SBAS127D) page13 Figure12. DOUT/#DRDY Timing, Please let me questions.

In a state in which to stop the CLK of the ADS1252, you can get the conversion result in SCLK?

(When the DOUT mode, CLK can use to stop?)

In particular,
After DOUT/#DRDY falls(Low) (t4), → after entering the 12CLK (t2 + t3), (fixed at the L or H) to stop the CLK.
Then (after t7), the DATA acquisition by issuing the SCLK at the timing of the host.
In this case, the state of the remains CLK is that stopped.
After Conversion-DATA acquisition, and then restart the CLK, wait for DOUT/#DRDY(Low).

Will you be able, such as?

Best regards

  • 0
    TI__Mastermind 44680 points

    Hi cafain,

    I'll be glad to help answer your questions!

    Both the SCLK and CLK signals are required to read the data from the ADS1252. You cannot disable the CLK signal after the conversion result and still read the data because the CLK signal is used, not only for sampling and acquiring the result, but also for controlling the digital state machine. If you notice on Figures 12-14, the CLK is shown as being continuous. Also, most of the timing requirements shown in table 2 are relative to the CLK period.

    Is there a particular reason why you want to disable the CLK signal, such as trying to reduce power consumption (for example)?

    Best Regards,
    Chris