Hello,
I have a couple of questions related to the ADS5294 ADC specifications (see snapshot below)...
(1) For the ADS5294, the data sheet latency states 11 sample clocks (see 8.7). However, it can't be determined from the information if this latency includes the time taken to serially transfer the data out of the device. I.e., there is a high-speed bit clock that transmits all bits within a sample clock interval (1 wire DDR mode). Is this clock interval included in the 11 number; or with the transfer included should I use 12?
(2) In the same data sheet table below, does the "Aperture delay" relate to the internal signal path delay as well as the internal sample clock delay?
I.e., to exaggerate, let's say the signal-to-be-sampled is applied to 2 ADC inputs on the same device. One of the inputs has a 5ns delay to ADC 1's sample and hold circuit and a 10ns delay into ADC 2's S/H.
Is that accounted for by the aperture spec, or does the spec only refer to the delay between the input clock and the sampling circuit (i.e., it does not say anything about the signal path "setup" time)? In my crude example, obviously the signals would be sampled at the same time (since the aperture delay variation is only 175ps), but at 2 points on the waveform that are 5ns apart due to the internal signal path having a 5ns delay difference to the S/H circuits...
Can you please clarify based on my example above what the "aperture delay" spec actually means?
Thanks in advance,
Bob
