TSW14J56EVM + TSW38J84EVM

Andre,

The number of samples should not affect the quality of the DAC output. The DAC simply playback the samples being transfered over the JESD204B link. I believe there may be something being impacted on the HSDC PRO or TSW14J56EVM.

If you can post the spectral plot of the two cases, it will help us analyze the situation.

-Kang

It could be due to the minimum sample requirements on the FPGA memory structure for the DAC playback firmware. For the DAC path on the TSW14J56 the sample size must be a multiple of 256 samples. 1024 and 2048 should work.

The IQ Multitone generator will force the # samples to a multiple of 256.

It is possible that as you change the number of samples, the actual center frequency of the coherent tone changes. This is due to the resolution BW of the signal as you use less points (Fs/N samples is as fine as you can resolve the coherent tone).

Ken.

Hi Kang and Ken,

Thank you for your answers.

In fact I have started working with these boards with a lower sampling rate, using the matlab dll libraries that you provide, and everything is working fine, except at the maximum sampling rate (1.2288 GSps). When I detected the problem, I have started doing tests directly with the HSDC I/Q tone Multitone generator, and I have detected that the output spectrum only makes sense with a #samples <= 1024. After concluding this, the same is also valid for the matlab case, i.e., if I send a signal with <= 1024 samples via matlab everything works.

Additionally, I realize that changing the number of points produces changes in the resolution bandwidth, that also may change the tones frequencies. However, when using periodic signals, which was the case when I was using the matlab interface, if the signal is periodic with 1024 samples it is also periodic with 2048 and any multiple of it. Nonetheless, as you may see in the captures below I do not think the problem is related with the signal generation, either in matlab or in IQ multitone generator.

As you requested, I send a capture of the DAC TSW38J84EVM configuration, and two pairs of captures of both HSDC with 1024 samples plus output spectrum, where the output is correct, and by last a capture of HSDC with 2048 samples plus a capture of the output spectrum. As you can see, the last one should not be like that.

 - TSW38J84EVM configuration

 

 

- HSDC Pro with 1024 samples + spectrum (ok)

 

- HSDC Pro with 1024 samples + spectrum (not ok)

 

 

Additionally, the board revision that I am using is revision B for both boards.

Thank you for your help and availability.

 

Best Regards,

Andre

Andre,

TSW14J56 revB cannot support a line rate of 12.288Gbps. The revB TSW14J56 can only support up to 10.3Gbps - this was a limit of the FPGA when the revB was released. A new TSW14J56revD was released last summer which supported up to 12.5Gbps.

Can you confirm if your TSW14J56 is a revB or rev D?

Ken.

Hi Ken,

Yes I confirm it is a rev. B.
If that is the reason, why does it works with 1024 samples?

Thank you.
Regards,
Andre

Andre,

I don't know why it doesn't work with the longer buffer - there could be memory access/FPGA fabric issues at that speed as the firmware was never compiled/timing closed at that rate - thats an FPGA question I cannot answer with any confidence. You can try with a slower lane rate <10.3Gbps to see if it works for other buffer lengths. It should be ok.

Ken.

Ken,

I have just finished to test  the same previous I/Q tone generator configuration with 614.4MSps, 732.28MSps and 983.04MSps, since those correspond to line rates < 10.3Gbps.  Right?

Additionally, I have tested with the following number of points: 1024, 2048 and 524288.

At 614.4MSps and 732.28MSps all the tests passed.

However at 983.04MSps both the test with 1024 and 524288 passed but the test with 2048 samples failed (see Figure below, where the spectrum should be similar to the above correct case). The failure seems again that occasionally exist some wrong DAC samples (the wrong tones vary). This is presenting a behavior different that with the 1.2288Gsps case, where every number of points > 1024 failed. In this 983.04MSps case only the 2048 fail, which I think is strange.

I have checked controlling via matlab and the behavior is similar, it failed with 2048 samples at 983.04MSps . Do you have any idea about what is happening now?

 

 

Thank you again.

 

Regards,

Andre

Hi again,

Considering that I have a TSW14J56EVM revB, I have only noticed now that I have installed the firmware in the zip file "slwc113", which is for the rev.D.
Can this be a problem? Is there any available firmware for revB?

Additionally, using the Matlab interface to control the HSDC to send data to the TSW14J56, is there any requirement about the number of points besides the maximum number? For instance, does the number of points has to be a power of 2 or something like that?

Thanks,
Regards,
Andre

Andre,

What zip file is the slwc113?

If you are using HSDC Pro software, it will recognize the TSW14J56 revB or revD based on the USB enumeration.  It will then configure itself to only load the appropriate firmware for the FPGA.  You do not need to manually load anything if you are using HSDC Pro.  The firmware is not static and is overwritten each power cycle.

There is an INI file in each details folder which shows the multiple of the length of the file needed.  Look in the "Device and File Info.ini"

For revB:

C:\Program Files (x86)\Texas Instruments\High Speed Data Converter Pro\14J56 Details  shows DAC Data Multiple = "256"

For revD:

C:\Program Files (x86)\Texas Instruments\High Speed Data Converter Pro\14J56revD Details  shows the same file length multiple.

However, other platforms like the TSW1400 will have multiple of 32 - this is all implementation specific to that platform.

Ken.

Hi Ken,

The slwc113.zip is the one that contains the following executable file''TSW14J56revD-3.03-windows-installer'.exe'.
And I have installed this .exe before the HSDC.

Thank you for the information about the number of points. I will check the .ini files. Nonetheless, I have shown you a case with 2048 points, which is multiple of 256 that is falling.

Regards,
Andre

Andre,

That exe just installs the .qar source project for the TSW14J56revD - it does not install anything into the FPGA. If you wanted to modify the TSW14J56revd firmware you can use this .qar file as a start. It does not impact the HSDC Pro in any way. The source folder is created here:
C:\Program Files (x86)\Texas Instruments\High Speed Data Converter Pro\Source Code

I don't know what could be wrong with the 2048 case. I will try it in the lab and see.

Ken.

Andre,

I just tried the case with 983.04M sampling rate, 1x interpolation with 1024, 2048, 4096 and all these cases look fine.  See attached.  I did have an issue if I tried to go to 512 or 256 - there was not enough samples to create a coherent 2 tone.

Ken.

TSW14J56_DAC38J84_diff length.zip

Ken,

Thank you very much for your fast answer.

In fact, your measurements are ok.

However, I have created complex two-tones instead of real. I am not sure about your HSDC implementation, but I assume that choosing real you are just using the I or the Q channel, while in complex both I/Q channels are used for the signal generation. Is that right?

Additionally, I noticed that I am using the GUI  v1.0 for the TSW38J84EVM revB configuration and  you are using the v1.1 of the GUI.

Do you think that is important?

Regards,

Andre

Andre,

Complex or real do not matter.

If you are using a TSW38J84, then use that GUI (this has controls for the TRF3722 device). If you are using the DAC38J84EVM then use the DAC GUI. The DAC GUI slac644a.zip is the DAC38J84GUI v1.1

Ken.

Hi Ken,

I did not noticed that you were using the DAC38J84EVM. I am using a TSW38J84 revB and the TSW3XJ8X GUI v1.0, which I think it's ok.

Is it possible for you to test with a TSW38J84EVM?

Do you have any other idea to justify the problem?

Thank you.

Regards,

Andre