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ADC12J4000EVM + TSW14J56EVM reference design

Tuan Truong46
Prodigy 110 points
Other Parts Discussed in Thread: ADC12J4000EVM, ADC12J4000

Hi,

I have just received the boards ADC12J4000EVM + TSW14J56EVM. We would like to do our own design based on this combination. Later on we would like to develop a design based on ZYNQ7000 SOC. For now, we would like to connect an Arria V Altera FPGA to the ADC via the JESD204B interface. Would TI be able to send me the FPGA Verilog or VHDL design files that are used for the evaluation kit, and if possible, for ZC706?

Thanks,

Tuan

  • 0
    TI__Genius 12965 points

    Tuan,

    Here is the link for the TSW14J56 Quartus project.  You will need a license from Altera if you want to recompile.

     

    Here is the link for the KC7 and VC7 projects.  We are working on a ZC7 project - that should be available in the next few weeks.

    Ken.

  • 0 in reply to Ken C
    Prodigy 110 points
    Thank you Ken for the files. We was able to capture and display the ADC data with the reference design.
    We now try to store captured data into DDR3 SDRAMs "in real time". According to our calculation, if we use a decimation factor of 4 and 4 JESD204B lanes, the data rate which is coming to the FPGA is 1 GSPS, each sample contains 32 bits (16 I and 16 Q) ==> 32 Gbps of raw data. If we use 4 DDR3 (bitwidth 16) @ 800 MHz, the maximum writing rate into the RAM is 800/4(quarter rate)*2 (double data rate)*16 (bit width)*4 (4 DDR3) = 25.6 Gbps. I wonder how we can handle a incoming flow of 32 Gbps given that the DDR3 writing rate is not that fast. Please let us know if we are missing or misunderstanding something.
    Many thanks,
    Tuan
  • 0 in reply to Tuan Truong46
    TI__Genius 12965 points

    Tuan,

    I didnt create the project, but if I recall correctly the DDR3 controller was instantiated with a wider bus than 16b.  I believe we may have split the 4x16 memory bus into 32b for RX and 32b for TX (transceiver mode).  This implies a 51.2Gbps per bank.

    Please check the DDR3 controller in the project.

    Ken.

  • 0 in reply to Ken C
    Prodigy 110 points
    Thank you Ken for the response!
    Regarding the quartus project, while opening the project I received many errors like "Error: Failed to restore: Altera_JESD204B/jesd204b_refdesign/syn/AVGZ_gen_jesd204b_120_SP2_external_memory/Jesd204b_mc_rx/synthesis/submodules/altera_jesd204_rx_descrambler.v". I am waiting for my Quartus II license. For now I'm in 30 days trial version of the software. I don't know if this is the reason why I can't restore the project. Can you give me a hint?
    Regarding the DDR3 instance, I found that you take 4 DDR3 (16 bit each) to form one 32b for Rx and one 32b for Tx. The data rate is actually 800/4*2*32 = 12.8 Gbps. I was not surprised with this, given that in www.ti.com you have already precised that the TSW14J56EVM can operate up to 12.5 Gbps. Our problem is to handle 32 Gbps flow from the ADC. We are thinking abount using 6 DDR3 (16 bit each) @ 800 MHz to handle this, but we are worrying about the PCB complexity! DO you think we can have another solution for this?

    many thanks,
    Regards,
    Tuan
  • 0 in reply to Tuan Truong46
    TI__Genius 12965 points
    Tuan,

    You will need to work with Altera on the Quartus errors. They are aware of our projects and can help with tool issues.

    We are already able to capture data from the ADC12J4000 in full bypass mode at 4Gsps. I'm not sure I understand your limitation. Are you capturing data from something else? Or multiple links?

    Ken.