Timing Issue in capturing QDR LVDS data from ADS42LB69 in FPGA

Hello ,

I am using ADS42lb69 ADC,I have connected the ADC in QDR LVDS mode to xilinx fpga kintex-7.My sampling rate is 160Msps. while capturing the QDR data in the FPGA data is not alligned properly so please share the VHDL code for QDR logic .

regards,

sureshkumar v