ADS62P49 Low sampling rate = low CLKOUT duty ratio?

Ross Petty

Other Parts Discussed in Thread: ADS62P49, CDCE72010

I'm driving an ADS62P49 CLKP/CLKM with a 20.5 MHz signal, believed to be close to 50% duty ratio. On the CLKOUTP/CLKOUTM, I am getting a 20.5MHz signal with a 13% duty ratio. I have set the Low Speed Mode via a register bit.

Couldn't find a spec for this in the datasheet (only listed "typical" duty ratio for a sampling frequency greater than 100 MSPS). Is this low duty ratio normal for a lower sampling rate?

over 9 years ago

0 jim s over 9 years ago

TI__Guru* 91947 points

Ross,

We are looking into this for you.

Regards,

Jim

0 jim s over 9 years ago in reply to jim s

TI__Guru* 91947 points

Ross,

What is driving your clock source? Does it meet the requirements in the table below? How are you terminating it?

Regards,

Jim

0 Ross Petty over 9 years ago in reply to jim s

Intellectual 300 points

I couldn't see any table in your post. The ADC clock is driven from a CDCE72010 PLL, there are 200 ohm resistors between the positive and negative clock rail and ground near the PLL output. Near the ADC input, 100nF capacitors in series, and then a 100 Ohm termination resistor between the positive and negative rail.

0 jim s over 9 years ago in reply to Ross Petty

TI__Guru* 91947 points

Ross,

With low speed mode enabled, internal logic that is used to keep the output clock at 50% duty cycle is disabled and what you are seeing is normal. This part was designed to be used in high speed mode unfortunately.

Regards,

Jim

0 Ross Petty over 9 years ago in reply to jim s

Intellectual 300 points

Okay, thanks.

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ADS62P49 Low sampling rate = low CLKOUT duty ratio?