I have an anomaly with a design using this part. I believe that it might be possible that we violated the t_SUCL constraint in the timing diagram. The chip controlling the interface to the DAC might have marginal timing on the relationship between the falling edge of SYNC and the rising edge of SCLK. Does anyone have any experience with the state of the DAC if this constraint is violated? Is it possible that the DAC interprets this write transaction with the bits left shifted by 1?
Design information:
The design updates the DAC at 10kHz. SCLK frequency is 19.4MHz. SCLK remains toggling all the time. SYNC remains low unless we are starting a transaction. The command value to the DAC during this anomaly was most likely 0x800 with the power down mode bits set to 0 for normal operation.
Based on the output of our design during the anomaly, we inferred that the output of the DAC is most likely a 5kHz square wave.
