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ADC12D500RF jitter cancellation

Kangbaek Kim
Intellectual 320 points
Other Parts Discussed in Thread: ADC12D500RF

I plan to clock the ADC at 500 MHz, and from 1Hz to 100kHz calculated jitter is ~330fs.  This obviously will limit the SNR of ADC12D500RF to ~48 dB when input analog signal is 2 GHz.  For this reason, I am going to feed both measurement and reference signals to ADC12D500RF to get some cancellation.

Do you know how much jitter cancellation I would get in this situation?

Thanks,

Kangbaek

  • 0
    TI__Mastermind 44680 points

    Hi Kangbaek

    I have not tried this approach before.

    Do you plan to sample your intended signal on one input and sample the ADC clock itself on the other channel? Then in post-processing the jitter effect will be removed?

    Or are you using the ADC clock to modify the input signal somehow?

    Best regards,

    Jim B

  • 0 in reply to Jim Brinkhurst1
    Intellectual 320 points

    My application is measuring phase difference between measurement and reference signals.

    I split 2 GHz signal.  One goes CH1 (measurement) of ADC after DUT and the other one goes to to CH2 (reference) of ADC straightly.

    I don't do anything special to remove the jitter.  I think the nature of simultaneous sampling will remove 'some' jitter because both channels share one clock signal.  Just do not know how much cancellation I can expect.

  • 0 in reply to Kangbaek Kim
    TI__Mastermind 44680 points

    Hi Kangbaek

    Thanks for the additional detail. The sample instant of the I and Q inputs will be very well correlated, so the additional jitter on your clock will cause both inputs to be sampled earlier or later than the ideal instant. This will provide jitter cancellation, but how much will also depend on how you are processing your reference and DUT signal data.

    Regards,

    Jim B