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Interfacing with AFE4403 watch EVM

Chi Zhang92
Prodigy 30 points
Other Parts Discussed in Thread: AFE4403EVM

Hi, I am trying to interface the AFE4403EVM with C and libusb (previously tried to read/write serial port as well). I now run into 2 problems:

1. When I try to set all timing registers to EVM defaults in the GUI software, 4 register changed contents:

  • LED1ENDC: want 0x000f9e, got 0x000f0e
  • LED1LEDSTC: want 0x0007d0, got 0x000000
  • LED1LEDENDC: want 0x000f9f, got 0x000f0f
  • ALED2CONVEND: want 0x000f9f, got 0x000f0f

Is there any restrictions on the sequence of writing the registers or any extra steps before I can changed the timing?

2. When I send the start ADC command to the EVM, I receive no response. However, if I send stop ADC command after sending start ADC command, I do have samples streaming to my PC, but the number of samples seems to be infinite rather than what I set. If I send another or more stop ADC commands, the sending will stop as expected. Simply sending 0x0d after the start ADC command does not have the same effects. I have check my code many times and could not figure out what is going on. I wonder if you have any ideas.

Thanks.

  • 0
    TI__Mastermind 49956 points
    Hello Chi,

    For the 2 issues,

    1. There are no restrictions on the sequence of writing to the timing registers.
    Are you able to write to these four registers (any other value than what you have mentioned) and read the values back correctly?

    2. Have you modified the firmware source code or is the EVM with the factory default firmware?
  • 0 in reply to Praveen Aroul
    Prodigy 30 points
    OK, I think I found the cause for the first problem. My code handles number to ASCII conversion incorrectly and '9' is translated to '@'.
    The second problem still persists. I have not modified the firmware and the watch works well with the EVM GUI.
    Is there any timing requirement? Currently I observed that if I do not sleep between reg writes, the firmware will hang.
  • 0 in reply to Chi Zhang92
    Prodigy 30 points
    Also I recorded all bulk transactions to the EVM, which all completed suceessfully. I also poll frequently to ensure messages do not build up at EVM side.

    afe4400evm_uart_write(): 06 0d
    afe4400evm_uart_write(): 02 30 30 30 30 30 30 30 43 0d
    afe4400evm_uart_write(): 02 32 32 30 30 30 30 30 30 0d
    afe4400evm_uart_write(): 03 32 32 0d
    afe4400evm_uart_write(): 02 31 44 30 30 31 46 33 46 0d
    afe4400evm_uart_write(): 03 31 44 0d
    afe4400evm_uart_write(): 02 30 31 30 30 31 37 43 30 0d
    afe4400evm_uart_write(): 03 30 31 0d
    afe4400evm_uart_write(): 02 30 32 30 30 31 46 33 45 0d
    afe4400evm_uart_write(): 03 30 32 0d
    afe4400evm_uart_write(): 02 30 35 30 30 30 30 35 30 0d
    afe4400evm_uart_write(): 03 30 35 0d
    afe4400evm_uart_write(): 02 30 36 30 30 30 37 43 45 0d
    afe4400evm_uart_write(): 03 30 36 0d
    afe4400evm_uart_write(): 02 30 37 30 30 30 38 32 30 0d
    afe4400evm_uart_write(): 03 30 37 0d
    afe4400evm_uart_write(): 02 30 38 30 30 30 46 39 45 0d
    afe4400evm_uart_write(): 03 30 38 0d
    afe4400evm_uart_write(): 02 30 42 30 30 30 46 46 30 0d
    afe4400evm_uart_write(): 03 30 42 0d
    afe4400evm_uart_write(): 02 30 43 30 30 31 37 36 45 0d
    afe4400evm_uart_write(): 03 30 43 0d
    afe4400evm_uart_write(): 02 30 33 30 30 31 37 37 30 0d
    afe4400evm_uart_write(): 03 30 33 0d
    afe4400evm_uart_write(): 02 30 34 30 30 31 46 33 46 0d
    afe4400evm_uart_write(): 03 30 34 0d
    afe4400evm_uart_write(): 02 30 39 30 30 30 37 44 30 0d
    afe4400evm_uart_write(): 03 30 39 0d
    afe4400evm_uart_write(): 02 30 41 30 30 30 46 39 46 0d
    afe4400evm_uart_write(): 03 30 41 0d
    afe4400evm_uart_write(): 02 31 35 30 30 30 30 30 30 0d
    afe4400evm_uart_write(): 03 31 35 0d
    afe4400evm_uart_write(): 02 31 36 30 30 30 30 30 35 0d
    afe4400evm_uart_write(): 03 31 36 0d
    afe4400evm_uart_write(): 02 30 44 30 30 30 30 30 36 0d
    afe4400evm_uart_write(): 03 30 44 0d
    afe4400evm_uart_write(): 02 30 45 30 30 30 37 43 46 0d
    afe4400evm_uart_write(): 03 30 45 0d
    afe4400evm_uart_write(): 02 31 37 30 30 30 37 44 30 0d
    afe4400evm_uart_write(): 03 31 37 0d
    afe4400evm_uart_write(): 02 31 38 30 30 30 37 44 35 0d
    afe4400evm_uart_write(): 03 31 38 0d
    afe4400evm_uart_write(): 02 30 46 30 30 30 37 44 36 0d
    afe4400evm_uart_write(): 03 30 46 0d
    afe4400evm_uart_write(): 02 31 30 30 30 30 46 39 46 0d
    afe4400evm_uart_write(): 03 31 30 0d
    afe4400evm_uart_write(): 02 31 39 30 30 30 46 41 30 0d
    afe4400evm_uart_write(): 03 31 39 0d
    afe4400evm_uart_write(): 02 31 41 30 30 30 46 41 35 0d
    afe4400evm_uart_write(): 03 31 41 0d
    afe4400evm_uart_write(): 02 31 31 30 30 30 46 41 36 0d
    afe4400evm_uart_write(): 03 31 31 0d
    afe4400evm_uart_write(): 02 31 32 30 30 31 37 36 46 0d
    afe4400evm_uart_write(): 03 31 32 0d
    afe4400evm_uart_write(): 02 31 42 30 30 31 37 37 30 0d
    afe4400evm_uart_write(): 03 31 42 0d
    afe4400evm_uart_write(): 02 31 43 30 30 31 37 37 35 0d
    afe4400evm_uart_write(): 03 31 43 0d
    afe4400evm_uart_write(): 02 31 33 30 30 31 37 37 36 0d
    afe4400evm_uart_write(): 03 31 33 0d
    afe4400evm_uart_write(): 02 31 34 30 30 31 46 33 46 0d
    afe4400evm_uart_write(): 03 31 34 0d
    afe4400evm_uart_write(): 02 31 45 30 30 30 31 30 31 0d
    afe4400evm_uart_write(): 03 31 45 0d
    afe4400evm_uart_write(): 02 32 32 30 31 31 34 31 34 0d
    afe4400evm_uart_write(): 03 32 32 0d
    afe4400evm_uart_write(): 02 32 30 30 30 30 30 30 30 0d
    afe4400evm_uart_write(): 03 32 30 0d
    afe4400evm_uart_write(): 02 32 31 30 30 30 30 30 32 0d
    afe4400evm_uart_write(): 03 32 31 0d
    afe4400evm_uart_write(): 02 32 33 30 30 30 30 30 30 0d
    afe4400evm_uart_write(): 03 32 33 0d
    afe4400evm_uart_write(): 02 33 31 30 30 30 30 30 30 0d
    afe4400evm_uart_write(): 03 33 31 0d
    afe4400evm_uart_write(): 02 33 32 30 30 30 30 30 30 0d
    afe4400evm_uart_write(): 03 33 32 0d
    afe4400evm_uart_write(): 02 33 33 30 30 30 30 30 30 0d
    afe4400evm_uart_write(): 03 33 33 0d
    afe4400evm_uart_write(): 01 2a 00 00 00 64 0d