Hello
I'm Alber as a FAE in Arrow Korea.
My customer are testing the RFADC(ADC38RF80) these days.
They reported strange operations at the SPI communications through the host(MCU).
following is the test conditions & results.
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test condition
CLKINP/M : 2949.12MHz
Test_1
1. clock signal ON
2. the SPI Communication did not operate corrrectly.
Test_2
1. Veryfied the SPI communication correctly at clock signal OFF
2. whole register of ADC32RF80 initialize
3. clock signal ON
4. they can be read only 0x70 at 'Main Digital Page' & 'JESD Digital Page' register, but they can read and write correctly at 'Decimation Filter Page'
Test_3
1. Clock signal ON
2. Clock signal OFF
3. 2. the SPI Communication did not operate corrrectly.
Test_4
1. Veryfied the SPI communication correctly at clock signal OFF
2. whole register of ADC32RF80 initialize
3. clock signal ON
4. Clock signal OFF
5. they can be read only 0x70 at 'Main Digital Page' & 'JESD Digital Page' register, but they can read and write correctly at 'Decimation Filter Page'
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So, they asked 2 things.
first, does the device exists any specific timing(or sequence) to be taken in the clock signal?
second, do you have any updated initialize procedure or datasheet and can you share it with me?
Thank you.
