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Utilities of ADCCLK for the VSP1221

Fabien15244
Prodigy 50 points
Other Parts Discussed in Thread: VSP1221

Hi,

I work on the ccd processor VSP1221 for a spatial application, i want to charaterize the "derive" of sampling with the temperature.

I want to know if the adcclk is use for the sampling. In the datasheet i read that it is the edge of SHP or SHD that is use to sample the video level or the reference level.

I have only a information with a timing with the falling edge of adcclk and the rising edge of SHD.

Thank you for your answer

Fabien

  • 0
    TI__Expert 3370 points

    Fabien,

    ADCCLK is not used to sample the CCD signals. The sampling of the CCD signal is controlled by SHD and SHP as described in the data sheet, page 6.

    ADCCLK is used to control the internal ADC conversion process. The VSP1221 uses a pipeline converter, which requires control of the timing between the ADC pipeline stages. The only exteranl function of ADCCLK is to control the output timing of the digital data as shown in the timing diagram on Page 6.

    ADCCLK should be kept to a 50% duty cycle with a minimum clock period of 46 nS and a minimum high or low width of 23nS. Please observe these requirements when doing any temperature testing.

    Regards,,

    Werner Metz

  • 0 in reply to Werner Metz
    Prodigy 50 points

    Thank you for your answer

    I have another question for the timing of the VSP1221,

    Now i need to know which edge or step of the ADCCLK start the conversion of the sampling reference and video level. I think it is a step or a edge of the ADCCLK during the pixel N+1 which start the conversion of the informations of the sampling of the pixel N.

    If you can answer me it will be a very important information for me. We use the VSP1221 for a spatial application!

    Best regards

    Fabien

  • 0 in reply to Fabien15244
    TI__Expert 3370 points

    Fabien,

    The falling edge of ADCCLK starts the conversion. This is the reason for the parameter Tadc_shd.

    Note that this is a pipeline converter, so in subsequent stages of the pipeline, both ADCCLK edges are used to perform conversions. That is the reason it is important to maintain as close to 50% duty cycle as possible.

    Regards,

    Werner Metz