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DAC8814 channel B is coupling logic switching noise from SDI (pin10)

NhatKhai Nguyen
Prodigy 30 points
Other Parts Discussed in Thread: DAC8814

Hi,

  I have a very high gain buffer OpAmp circuit on all for 4 channels of DAC8814. All three channel output are stable, but the channel B was having a glitch that correlate to the logic switching on the SDI pin10. I had try to add 10kOhm in series with this SDI logic signal, but the magnitude of the glitch on channel three have not degraded. So I thinking it is coupled internally in side the IC after the internal buffer circuit of SDI. I would like to know if the IC designer know about this issue? and would like to know if TI have any plan for correct and release in next revision of this IC?

Khai,

  • 0
    TI__Genius 10615 points

    Hi Khai,

    The digital feedthrough specification for all channels is listed in the electric characteristics table as 1 nV-s.

    Adding the 10 kΩ would have reduced the feedthrough of the device. Since it did not have any effect I suspect it may have something to do with the layout of the board. Are you by any chance using our EVM to test this? If you are using your own board, I can offer a layout review to see if there may be any issues there. If you would rather share this privately, can I contact you to your E2E registered email?

    If you have access to a few extra device. A simple test would be to lift the digital pins from the DAC8814 such that the output is only affected by the layout feedthrough.

  • 0 in reply to Eugenio Mejia
    Prodigy 30 points
    Hi Mejia,
    I was suspect the layout problem too. However, I did a test on it. The test were disconnected the SDI signal to the IC, and let everything run as normal. What I had see from this test is that, there is no glitch in any of the 4 channels output of OpAmps.

    Furthermore, if this is a layout problem only, then must be the SDI logic line. If logic SDI layout cause problem, then adding a large resistor series on the SDI logic line would slow down the transition of SDI line, and would reduce the pickup amplitude. But I don't see that happening. This lead me to the conclusion is that the internal buffer of SDI internally coupled to nearby analog pin so that external series resister did not affect this interval logic transition.

    I have 5 "identical" sub-circuit using five DAC8814s on the board. These five are behave exactly the same (glitch on channel B only). I thinking the SDI pin is next to the Feedback pin for the OpAmp. In your datasheet, it were driven by the external buffer OpAmp output, that may help to avoid the glitch problem. But in my circuit, I don't use them so I can get higher gain than 1 (very high gain ~600x).

    The logic signals are not overlapping any of the analog signals across the layers on my board. They are in difference layers and are separated by a solid ground layer between them. The IC on top layer where all the analog signals are.

    I do not have EVM board.

    Khai,
  • 0 in reply to NhatKhai Nguyen
    TI__Genius 10615 points
    Khai,

    I see what you mean. Can you share with me a snapshot of your schematic along with a capture of this glitch? I would like to try to reproduce this in my lab. I would still be interested in taking a look at the layout. While crossing digital traces over analog traces is certainly the biggest cause for digital coupling, it can sometimes be observed even through GND planes due to return current paths being coupled.

    This is certainly not something we have observed in the past with our devices, but the physical placement of the SDI pin next to the RFB_B pin does make this more likely to occur. Thank you for being this to our attention. If you can share some of the requested information, it will help us get to the bottom of this more quickly.