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ADS1675 control problems

Albert Llimos
Prodigy 80 points

Other Parts Discussed in Thread: ADS1675

Hi,

I have recently purchased the ADS1675REF board and I have reprogrammed the FPGA board in order to control the ADS1675 board as I wish. However, after reading the ADS1675 datasheet and trying to write the code to control it I haven't been able to do it, and I can't get the DRDY signal to high, so I guess my understanding of the datasheet may be wrong.

After supplying voltage to the board I have set all the control values (DRATE, SCKL, LL_config...) to the desired value. After this power up, and from what I understood in the datasheet, the chip will send a DRDY pulse to prove that it is ready for starting conversions. After that, an start pulse can be send to the converter and whenever the DRDY signal is high again it means that I can get the data with the following 24 SCLK clock cycles.

However, after the power up I have tried waiting for the DRDY pulse, but it never happens. Also, I have tried sending a start pulse on the power up but I still don't get a DRDY pulse back. Do you have any idea of what am I doing wrong?

Thank you very much.

Albert

  • 0
    TI__Guru**** 182671 points
    Hi Albert,

    Have you verified that the Opal Kelly board is sending a clock to the ADS1675REF board? The DRDY pulse you describe above is issued only after the ADS1675 achieves a PLL lock. If there is no modulator clock (check the output of U6, pin 4 referenced to GND), there will not be a PLL lock and the DRDY pulse will not appear regardless of the state of the START signal.