DAC38J82 Power vs JESD lanes

Eric Zuber

Other Parts Discussed in Thread: DAC38J82

Hi - have a power sensitive application where we are using DAC38J82. The total JESD input rate required for the mode we are using is 9.6 Gbps. For this rate, we could design with 1, 2 or 4 JESD lanes - would you please provide estimates of Ivddt09 and Ivddr18 for each mode to allow us to perform a system level power trade? (the FPGA transmitter is actually lowest power in 2 lane mode)

Thanks - Eric

over 9 years ago

0 jim s over 9 years ago

TI__Guru* 91947 points

Eric,

We are looking into this. What application is this for?

Regards,

Jim

0 Eric Zuber over 9 years ago in reply to jim s

Prodigy 220 points

Thanks - this is for a military communications system...

0 jim s over 9 years ago in reply to Eric Zuber

TI__Guru* 91947 points

Eric,

Figure out what the DAC sample rate will be for each of these modes and use tables 31-42 of the data sheet to determine what the power draw will be.

Regards,

Jim

0 Eric Zuber over 9 years ago in reply to jim s

Prodigy 220 points

The figures do provide power draw for many different DAC operating modes vs sample rate and interpolation, but it looks like all assume a 4 lane (LMF=421) JESD-204B interface based on the 'unless otherwise noted' figure notes and the lack of any specific JESD configuration call-out in any of the tables. I am specifically looking for power differences with a fixed DAC mode and sample rate, but different JESD Lane widths.

0 jim s over 9 years ago in reply to Eric Zuber

TI__Guru* 91947 points

Eric,

The DAC Serdes will use about 80mW/lane at 12.5Gbps. I am searching how much is related to each power supply and what this would be at 9.6Gbps.

Regards,

Jim

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DAC38J82 Power vs JESD lanes