• State
  • Locked Locked
  • Replies 10 replies
  • Subscribers 48 subscribers
  • Views 1085 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

cyglone 5 gt interface for ads5263

Luca Meloni
Intellectual 570 points

Other Parts Discussed in Thread: ADS5263, ADS5263EVM

Hello.
Is there a ready block to connect the cyclone_gt to the adc ads5263?
The device ads5263 have 4 channels analog input, and each channel has 2 ddr lvds  outputs lanes.

then i have:
1 bitclock wire (ddr)
1 frameclock wire.
2 lvds lines for each channel.

Can i use alt_ddio or alt_lvds_rx megafunctions?

Regards, Luca

  • 0
    TI__Mastermind 18285 points

    Luca,

    I'm assigning your post to the correct applications engineer.

  • 0
    TI__Genius 12025 points
    Hi cyglone,

    How are you?
    Thanks for using our ADS5263 device.
    We are looking into your questions.
    We will replay to you very soon.

    Thank you!

    Best regards,
    Chen
  • 0 in reply to Chen Kung
    Intellectual 570 points

    oopss.

    cyclone5gt, i must write

  • 0
    TI__Genius 12025 points
    Hello Luca,
    Thanks for using ADS5263 device.
    Our ADS5263EVM is connected with TSW1400 board to capture
    Frame Clock, Bit Clock and Output Data.
    TSW1400 uses Altera Stratix used for LVDS data capture.
    Please compare any difference between Stratix and CycloneVgt.
    Assume you need the highest clock speed 100MSPS sampling rate for using ADS5263.
    If you want only use 1-Wire mode (Data Sheet page 37), then
    you need to use FPGA can reach Data Rate = 16*100MHz = 1600Mega data per second
    that is Bit Clock = 8*100 MHz = 800MHz
    Or if the FPGA can not run such fast data rate,
    you can choose 2-Wire mode (Data Sheet page 38), then
    the Bit Clock = 4*100MHz = 400MHz
    Please make sure CycloneVgt can fit one of these requirements.

    Thank you.
    Best regards,
    Chen
  • 0 in reply to Chen Kung
    Intellectual 570 points

    I use 2 wire mode and so i have 800Mbps stream data (for 1 wire) and 400MHz bit clock DDR.

    The bit clock is routed from ad5263EVM to TI adc to HSMC adapter,to the hsmc portA of cyclone 5 gt dev board (at pin H_17). This pin is a clk input of PLL.

    The frame-clock is routed to lvds pin of fpga F_17.

    This pin is NOT a pll clock input pin. Is it a problem?

    I would use the lvds rx function, but I do not know if I can use it in this case.

    Do The lvdsrx megafuntion work to DDR data rates?

    Can i do without the frame clock?

  • 0 in reply to Luca Meloni
    TI__Genius 12025 points

    Hi Luca,

    Thanks for using our ADS5263EVM.

    For details of using the fpga to capture ADS5263 output signal,

    I believe both Bit Clock and Frame Clock are necessary to be used,

    also I will need to find the fpga expert engineer for the detail questions.

    Thank you!

    Best regards,

    Chen

  • 0 in reply to Chen Kung
    Intellectual 570 points

    Ok, after a week i have resolved.
    The ads5263 is now ready. I use 8 channels alt_lvds_rx at 800 Mbps, for implement 4 channels 16 bit at 100Msps
    I do not use frame clock, but the bit align function of serdes.
    Best regards, Luca

  • 0 in reply to Luca Meloni
    TI__Genius 12025 points

    Hi Luca,

    Sounds good to know you got the data align function can do the same thing as Frame clock.

    Here is our good document for the LVDS capture (sbaa205).

    www.ti.com/.../litabsmultiplefilelist.tsp

    Thanks for using ADS5263 device.

    Thanks and best regards,

    Chen

  • 0 in reply to Chen Kung
    Intellectual 570 points

    Another question..

    If the ads5263 is configured as 16 bit 2'complement, what is the maximum (an minus) range of the 16 bit word?

    I think 0x7FFF (max),  0x0001(the one), 0xFFFF(the one negative),  0x8001(min).

    Is it correct?

    The word 0x8000 NOT exists? right?

    Regards

  • 0 in reply to Luca Meloni
    TI__Genius 12025 points

    Hi Luca,

    When you are using 2's complement mode, the data serial output will be:

    (assume MSB FIRST is on):

    0x7FFF (max) = 32767 (in dec)

    ...

    0x0001 = 1 (in dec)

    0x0000 (zero) = 0 (in dec)

    0xFFFF = -1 (in dec)

    ...

    0x8000 (min) = -32768 (in dec)

    Thank you!

    Best regards,

    Chen