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Configuration of the DAC38J84

Other Parts Discussed in Thread: DAC38J84

Hello,my name is Liu An,I'm a student from the University of Chinese Academy of Sciences.Recenty I'm in a project using DAC38J84 and I have some questions about the configuration of this chip.I really hope to get your help and please read my quetions patiently,even though my English is poor.And it's also the first time I write so many in English,sorry for my Chinglish .The questions are as follows:

1.About the step 12 in the initialization of set up.In the datasheet,chapter 8.3,said that the user check the lock status of SerDes PLL by alarm_rw0_pll and alarm_rw1_pll, which are the bit3 and bit2 in the config 108 respecty.

a.Can I read this two bits after I config all the registers? I mean check config108 after step 15.Will this effect the result of the status of SerDes PLL ?Will this make me get the wrong information from the related register?

b.The datasheet describe that A false alarm is generated at startup when the PLL is locking. User will have to reset this bit after start to monitor accurately.

  (1) So when I carry out the Step 12,I need to clear the config108 and then read it?

  (2)Write "0"to clear it or write "1" to clear it?

  (3)If I reset the chip,will the write to clear registers like config100-108 turn into their default value?

  (4)Read config108 immediately after write clear it will be OK?

c.If I make sure that I perform the right configuration of all the registers,can I do not carry out the Step 12? I mean if I'm sure that the correct confgration will lock the PLL, I will not verify its status

2.About alarm related registers

a.the config4/config5/config6 is about the alarm_mask,and the default value means to mask the alarms.If I read the alarm related registers config100-108 under the situation that config4-6 are in their default value,I will get what? "1" or "0" or what else?

b.In config5, the defaut value is 0xFFFF,which means  the alarms of status of SerDes PLL are masked.But in the Chapter 8.3,the initialization set up,Step 12 says to check the  status of SerDes PLL. These are contradictory.Because before step12,there are no instructions that tell the users to config register5,or register4-6. And I will read the alarm status when the alarm is masked.

c.If the alarm is occured,will this effect the output of DAC?The DAC will give the wrong output or the output will be zero always?

d.Do the alarm registers like config100-108 must be read when the txenable is high?

3.About the TXENABLE.
The datasheet says to enable analog output data transmission, set sif_txenable in register config3 to “1” or pull TXENABLE terminal to high.  To disable analog output, set sif_txenable to “0” and pull CMOS TXENABLE terminal to low. If I want to enable it,which method has higher priority? If the pull the terminal to high and do not config register config3,will it be enabled?Or  I set the sif_txenable to"1" and make the terminal to low,will it be enabled?

4.The datasheet mention the "SIF" a few times,what dose this mean? Serial Interface?

5.Before I seek for help in E2E,I connect the technical support workers in Asia and reflect some questions about the datasheet.They admited that there are wrong instruction in the datasheet,they said they will reflect this to American official.But I can't find any correction tables in the Internet.Can you offer me the newest datasheet or the know wrong instructions?

Above all are my quetions.Because not adding JESD204B in project,and now I just use the FPGA to config the DAC,I can't observe the output of the chip,I can't solve some question by doing some experiments.

Before I post this "blog" or email, I try to connect the technical support workers in Asia.But they said that they can't give me the help.I try to beg them to help me connct the American official and reflect my question, they reject me and give me the link to E2E.I'm sorry that my English is poor and  may not explain my question clearly.But I hope you experiencd engineers can help me and give me some suggestions,for my adviser can't give me help ,either thetechnical support workers in Asia .

This is the first time that I have been in a engineering project,and I have no experience at all.This problems really confuse me and frustrate me.If you are the works of TI,I hope you can you reflect my question,and revise the datasheet . I hope I can attach the company the attention, even I'm just a student or nobody.

Looking forward to your reply,my email is 1176339383@qq.com.You can connect me in E2E or by this email.I hope we can become friends.

Thank you,

Best wishes

Liu An

  • Liu An,

    We will respond to your questions shortly.

    Are you trying to implement the SPI using the FPGA?  Have you evaluated the DAC EVM yet in the TI environment?  If you have not I would highly suggest you do this first to familiarize yourself with the DAC before attempting to do everything on an FPGA.

    The TI evaluation platform will use the PC based GUI (USB) and the TSW14J56 digital pattern generator along with HSDC Pro software.

    Ken.