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DAC3484 Pattern Checker Test

Ananth Krishna
Prodigy 100 points
Other Parts Discussed in Thread: DAC3484

Hello . I am working with DAC3484 and trying to do the pattern checker test by sending data in through an FMC with FPGA . Here is my Current status

1. no alarm is generated at iotest-alarm in config 5 and reading 0000 in config 4 when I am sending in all 1s and pattern all 1s.

2. no alarm is generated at iotest-alarm in config 5 and reading 0000 in config 4 when I am sending in all 1s and pattern all 1s.

I am using ODDR to generate Data on both clock edges and OBUFDS to give the LVDS output from FPGA to the DAC .

I have a simulated waveform of the input format I want to send , and which has been generated by my code

here data is the output to the FPGA and sys_clock_200MHz is the input to the OBUF which generates the DATACLKP/N

and frame_op acts as  input to OBUFs which generate both FRAMEP/FRAMEN and SYNCP/SYNCN

Is there anything wrong with the below format of giving input , or might be there something else I might be missing ?

Any help regarding this would be really appreciated

TIA

  • 0
    TI__Guru* 78884 points
    Ananth

    As I have mentioned in the other post, have you checked the following:
    1. setup/hold time of the DATACLK with respect to the DATA. Keep in mind you may adjust config36 setting to adjust the setup/hold time of the data capture on the LVDS bus.
    2. check the physical level (voltage and time) using oscilloscope. Make sure the IO level assigned for your FPGA is actually LVDS level. Make sure the timing assigned is indeed correct as well.
    We cannot support anything related to your verilog code, but we can support you once you can confirm that the scope shot of these signals are indeed correct. Attaching the scope shots of these measurements will also be helpful.

    -Kang