Hi egineers:
I have some questions about the configuration of the DAC PLL of the DAC38J84. My requirement is to use DACCLKP/N as the reference clock of DAC PLL and the output clock of PLL is 1.2GHz(DACCLK).And P is 4,M is 2 My questions are as follows: 1.About config51. a.If I choose the H-Band,that is the bit15 is 0,then how can I choose pll_vco to control the frequency range of vco?For example,I chosse pll_vco to be 011010,and according to the equiton (1) on Page 58,I get the frequency of VCO is 4.8GHz.Here comes the question,the frequency range is 4.44GHz to 4.8GHz or 4.8GHz to 5.6GHz? b.How can I config bit14:9?According to Page 60,the bit14:9 controls the charge pump current,and charge pump current is related to P*M ratio.Can you tell me how to compute how much charge pump current I need ?It is acorrding to the arguments P and M? c.The equition (1) on Page 58 just gives the relationship under the condition pll_vcoitune="11",what about other values?"00","01","10"?How to choose pll_vcoitune 2.If I choose to use DACCLKP/N to be the reference clock to be SerDes PLL divider input clock and bypass the DAC PLL.When I read the register 108 after all the configuration,which value I will get from the config108 bit0 that reflects the lock status of DAC PLL? I hope you can help me.
Thank you!
Best wishes!
