This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Hi,
My customer is using ADS52J90EVM with TSW14J56EVM.
He has saome questions about HMC-DAQ GUI.
Could you answer the following question, please?
Q1: What does the below picture window mean at JESD204B interface?
-> For example, What is ADC Output Data rate?
Q2: Could you please give me User's Guide at JESD204B interface of HMC-DAQ with ADS52J90EVM and TSW14J56EVM?
Best regards,
Shimizu
Shimizu,
Yes, 20x is the MIF value. Under
C:\Program Files (x86)\Texas Instruments\High Speed Data Converter Pro\14J56revD Details\MIF Files
, you can see the supported values of the TSW EVM. Additionally, You will need to change the ini file parameter found here
C:\Program Files (x86)\Texas Instruments\High Speed Data Converter Pro\14J56revD Details\ADC files
Change the two parameters belows and consult the other ini files to find the correct Fabric PLL value, for instance 40x mif should be 0x080202
MIF Config= 0.5G to 8.0G:RX:RX_PMA_x20
\\List of Lane Rate Range,PLL Type and their MIF File names that needs to be configured,separated by ":"
\\These MIF Files need to be present under MIF Files Folder
Fabric PLL Counter = 0.5G to 8.0G:0x080404
Then, press F10 when using the HMC-DAQ GUI. Using the Clock Outputs page and the sysref page, configure the correct clock ratio. I believe Ch0 DCLK divider is GTX and CH2 is the ADC_CLK. This ratio will change with different MIFs.
Condition 1 is already consistent with the Quick Setup Preset for 12x,12b mode and external clock source. This requires a 240MHz GTX for 20x MIF.
Condition 2 is simply N=10 and change the ext clock source, right?
Save your customer cfg with the save configuration button in the top left. Then modify the cfg to your liking.
TI Healthtech 16 channel AFE JESD204B Training.pdf
For 16ch mode, Clock Ratio is always GTX/Fs = (20/MIF) *N'/L
Shimizu,
Q1: No, there is no fractional divider. You will need to use a 240 MHz clock and then divide down, it seems.
Q2: This is from the Altera IP limitation.
Q3: This is an FPGA rule, but it is similar on Xilinx and Altera.
Thanks,
Chuck