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ADC12J4000 ADC TEST PATTERN MODE

Other Parts Discussed in Thread: ADC12J4000EVM

Hi sir,


We are trying to test the ADC Test pattern mode. But we are not observing the pattern as mentioned in table no 33.

We tested the JESD Test pattern (Ramp, K28.5, Repeated ILA)  with this test cases we are able to see the test patterns in FPGA.

The following registers settings has been done ,

1. enabled ADC Test pattern (0x058) - 0x06

2. 0x202-00

3. Foreground calibration enabled.

I have some doubts in register mappings,


1. For 0x058 Register - bit 2 - Either 0 (or) 1 to enable ADC Test pattern

2.find attachment for ADC Register configuration. Pls check whether any modifications are required to enable ADC Test pattern.

Regards,

bharath


0x002100
0x002101
0x02011E
0x00003C
0x000200
0x001000
0x00209D
0x002240
0x002300
0x002400
0x002540
0x002600
0x002706
0x0028BA
0x002994
0x002AEA
0x003000
0x003280
0x0033C3
0x00342F
0x0035DF
0x003600
0x003745
0x004004
0x005184
0x005200
0x00535C
0x00541C
0x005592
0x005620
0x005711
0x005806
0x005A00
0x006603
0x006700
0x006A00
0x006B20
0x020010
0x020200
0x020300
0x020400
0x020500
0x0206F2
0x0207AB
0x020800
0x020C00
0x020D00
0x020E00
0x020F00
0x021000
0x021100
0x021200
0x0213C0
0x021400
0x021500
0x0216FF
0x021700
0x021800
0x021900
0x021A00
0x021BC0
0x021C00
0x021D00
0x021EFF
0x021F00
0x022000
0x022100
0x022200
0x0223C0
0x022400
0x022500
0x0226FF
0x022700
0x022800
0x022900
0x022A00
0x022BC0
0x022C00
0x022D00
0x022EFF
0x022F00
0x023000
0x023100
0x023200
0x0233C0
0x023400
0x023500
0x0236FF
0x023700
0x023800
0x023900
0x023A00
0x023BC0
0x023C00
0x023D00
0x023EFF
0x023F00
0x024000
0x024100
0x024200
0x0243C0
0x024400
0x024500
0x0246FF
0x024700
0x024800
0x024900
0x024A00
0x024BC0
0x024C00
0x024D00
0x024EFF
0x024F00
0x025000
0x025100
0x00500E
0x02011F

  • Hi bharath

    Are you using the ADC12J4000EVM, or a board of your own design?

    On the ADC12J4000EVM, the JESD204B lane polarities have been inverted with respect to the standard FMC mapping to ease routing and improve signal quality. The capture firmware in our TSW14J56EVM and similar tools is set to compensate for the polarity inversion.

    I'll review the register settings and let you know if I have additional questions or comments.

    Best regards,

    Jim B