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Problems with ADS1278:

Andrew Dane
Prodigy 10 points
Other Parts Discussed in Thread: ADS1278

I'm having some trouble getting the ADS1278 to function properly and I was wondering if anyone could give me some advice.

In SPI mode with multiple channels powered up and data coming out of D1 in 'dynamic' TDM the output is all garbage. With the same setup and only one channel powered up I sometimes get the reading I am expecting and sometimes get garbage (If I use an input to detect a voltage level that I am slowly increasing the output sometimes gives me the right value but mostly undershoots this value- in all what should look like a ramp looks like step pyramid with spikes that form the intended ramp; sorry if this is hard to visualize, another way of putting it is that if you were to look at the envelop of the output, the top is the intended ramp, while the bottom is a step function).

 

Additional details:

I am keeping the ADC 'unsynced' until I want to read a sample. I then bringing sync high, wait at least the appropriate settling time and then begin to pulse the serial clock.

I am operating in low speed mode, CLKDIV =0, with a 5Mhz clock (not 5.4 as desired per datasheet); the serial clock does not exceed 1Mhz.

I am using the input single endedly as per page 24 of the data sheet (AINP is varies between 0V and 2.5V while AINN is held at ground). [I know the 1278 wants a 2.5V common mode, I was just hoping that because it says I can use it single-endedly that it would not completely ruin performance ].

One thing that may be the cause of my troubles: my SCLK and the 5Mhz clock are not synchronized so I may be at times violating some timing requirement.

 

Any help on figuring out what the major factor contributing to my ads1278 malfunction would be appreciated.

 

thanks,

Andrew

 

 

  • TI__Mastermind 43915 points

    Hi Andrew, 

    Sorry for the delayed response. It sounds a lot like your problem has to do with how you are driving the ADC inputs and the ramping you are seeing is the "slow" charging of the sampling capacitor on the modulator. The reason I say "slow" is because the modulator samples very fast and requires that you have an amplifier in order to drive the input. I have a couple of questions for you: What are you using to drive the inputs of the ADC? Can I see a schematic of your setup? That will help me understand your test setup and design. 

    In your design, you are using a 5MHz fclk and an SCLK a little less than a MHz. Having them out of phase or 'unsynced' will not create the behavior that you are seeing. With clocks out of phase, your more likely to see higher noise but still within spec. 

    Vcom should not be a problem if you are using the ADS1278 in single ended mode. Just note that in your current configuration, you are losing half of the ADC input range.

    Regards,

    Tony Calabria