Other Parts Discussed in Thread: ADC121S101-Q1, ADC121S021
Hello,
ADC121S101-Q1 INL, DNL, Voff and GE is specified at Fsclk is 10MHz to 20MHz as follows.
But Clock frequency of Recommended Operating Conditions is 25kHz to 2MHz.
Customer want to use low SCLK frequency because they use with digital isolator.
Delay of isolator is 58ns max so we can’t use 10MHz clock. There is 58ns x 2 delay from SCLK at MCU to SDATA at MCU.
Could you explain how INL, DNL, Voff and GE is degrade if we use 2MHz SCLK(for example).
Best Regards.
