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ADS1299 Unexpected DRDY behaviour above 250SPS

Hi,

I am testing a custom ADS1299-based PCB and I am seeing strange behaviour on the DRDY pin above 250SPS. My design uses bipolar power supply. SPI CLK is currently at 1MHz. Data is transfered to MATLAB using a USB to Serial (FTDI) and communication is working flawlessly.

Here is a screenshot of the internal test signals working at 250 SPS (CONFIG1 0x96)

And the corresponding Logic Analyzer acquisition :

Here is a screenshot of the internal test signals at 500 SPS (CONFIG1 0x95) :

And the corresponding Logic Analyzer acquisition showing unexpected toggling of the DRDY pin after the first couple of samples:

If anybody would have a clue about what is going on with the DRDY pin.

Best regards

  • Hello Mikael,

    It looks like the host is not able to shift all the data out from one conversion before DRDY falls low for the next. The result is corrupted conversions. DRDY looks strange because some DRDY edges fall in the time that the host is still toggling SCLK from the last conversion. In addition, DRDY returns high on the falling edge of SCLK which in some cases may be too fast for the scope to have captured the event at all.

    The fix is to further streamline the SPI routine to trigger as quickly as possible after DRDY falls low and to use as fast an SCLK frequency as you can.

    Regards,
    Brian Pisani
  • Many thanks Brian, I've implemented Change Notice Interrupts on the MCU pin connected to DRDY, instead of polling for the pin status and I now get up to 1kSPS without issues. However I need to further improve my SPI routine as it is too slow at the moment to handle sampling rate at 2kSPS and over. The issue is that I am doing some slight data processing in the routine (conversion from INT24 to INT32, and even to floating point). It would be much more appropriate for the computer to handle all this simple processing.

    Best regards,

    Mikael

     

     

  • Hey Mikael,

    Agreed. I'm not sure what kind of MCU you are using, but if it has capability to do DMA transfers with peripherals, this could open up some core bandwidth for processing while the DMA engine handles the communications.

    Brian