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ADS1281 Continuous Sync

Eugenio Scarpa
Prodigy 70 points
Other Parts Discussed in Thread: ADS1281

Hello everybody,

I've been reading the discussion on the following link (https://e2e.ti.com/support/data_converters/precision_data_converters/f/73/p/227253/801367) concerning the usage of the Continuous Sync mode on the ADS1281.

Here further I'd like to ask more precise guidelines for applying this method. The system is set as follows:

- 6x ADS1281 each one on a separate board;

- each ADS1281 is feed with a 4.096 MHz independent oscillator;

- 1KHz Sync signal sent from an FPGA module with which all the ADC communicate for serial configuration and data communication.

The previous setup was to propagate a single master clock from the FPGA to all the ADC. However, the precise frequency of 4.096 MHz couldn't be obtained on programmable logic and thus when trying to apply the Continuous Sync mode, the ADS1281 used to restart the sync process even if the Sync signal was sent at an integer multiple (1) of the data rate.

Thanks in advance for your help, I hope I was clear enough in my setup explanation.
Eugenio

  • 0
    TI__Mastermind 44680 points
    Hi Eugenio,

    Welcome to the TI E2E forums!

    Depending on your application, the continuous-sync mode may or may not be helpful...

    Ideally, all ADCs would run off of a single-clock to keep them all in sync. However, should one ADC get out of sync (perhaps due to a glitch that only affected that ADC), the continuous-sync mode provides a "repairing" mechanism to get all devices back in sync (the down-side is that the out-of-sync ADC doesn't provide data while the digital filter is settling). In this way, you have a lot of confidence that all ADCs are in sync; and should one get out of sync, the continuous-sync mode provides a way to havea self-repairing sensor network that keeps all ADCs in sync.

    In the case where each ADC runs off of a separate clock, each ADC will operate at a slightly different master clock frequency. Hopefully, these frequencies are close and all the ADCs stay in sync for a while; however, it will only be a matter of time before an ADC needs to re-sync. Using continuous-sync mode will help keep all the ADCs in sync. However, keep in mind that a re-sync will require that the ADC's digital filter settles again (so for a period of time that ADC will not provide data). If this is an acceptable trade-off in your application (such as in the case where each ADC is part of a sensor network that can handle gaps in data when only one or a few nodes are down), then continuous-sync mode may be useful to you. However, if a gap in data is hard to manage or unacceptable AND/OR the oscillators are prone to drifting (such that re-sync occurs often and there are large gaps of missing data), then continuous-sync mode may not be the best option.

    I don't see any issue with your system setup; however, I would keep in mind that depending how often ADCs get out-of-sync, there could potentially be large gaps in data. So I would most likely use continuous-sync mode only if it was really important to ensure that all ADCs were in sync. Otherwise, I might prefer to collect data (avoiding data gaps) and deal with data that was out of sync.

    I hope that helps!

    Best Regards,
    Chris
  • 0 in reply to Christopher Hall
    Prodigy 70 points

    Hello Chris,

    thank you so much for your quick and very clear explanation!

    As I start again to read your reply, I would therefore like to ask you a further simple yet not so immediate question: what is the appropriate setup the continuous sync mode was thought to be used in? Or, equivalently, why should the continuous sync mode be used if the downside is the risk of reset the filters and therefore cause a loss of data? Is it then just a trade-off of precision against data?

    Furthermore, concerning the usage of a single master clock: in the current system setup, the FPGA indeed generates a single 4.000 MHz and propagates it to all the 6x ADS1281. ADCs are however piloted separately, meaning that each one communicates data to a separate custom module in the FPGA. In this way, data are obtained in a parallel fashion before being processed, reducing the latency from acquisition to elaboration. This master clock frequency, however, brought eventually to a not-so-precise data rate (e.g. 988 Hz instead of 1KHz as default configuration). Is it because of the smaller master clock frequency?

    Thank you in advance, again!
    Eugenio

  • 0 in reply to Eugenio Scarpa
    TI__Mastermind 44680 points

    Hi Eugenio,

    The continuous-sync mode is intended to be used when it is infrequent or unlikely for the ADCs to be out-of-sync. In that case, continuous-sync mode gives you extra confidence that your data is coming from synchronous ADCs. Without this mode, the ADCs would initially be in sync, but could potentially drift over time and get out-of-sync without any indication. Yes, there is the trade-off that while the ADC is re-synchronizing it is not providing data, but this feature was intended for a sensor network that could fill in this gaps from other nearby synchronous sensor nodes.

    The answer to your second question is "yes'. The ADC's data rate is a direct function of the master clock frequency. By providing a 4 MHz clock instead of the nominal 4.096 MHz clock frequency, the data rate will decrease by a factor of 4/4.096 ~= 0.976.

    Best Regards,
    Chris