ADC12J4000 JESD Short Pattern Test

Hi All,

I am trying to establish the JESD data link between FPGA and ADC12J4000 using evaluation boards (KCU105, TSW14J10EVM, and ADC12J400EVM).

I am using the [JESD204B TI Reference design] provided for TSW14J10EVM.

In Ramp test mode, I am able to see correct data on all lanes, but in Short Pattern test mode I notice something different than expected according to the ADC12J4000 datasheet. 

ADC is running at 4 GSPS in Bypass mode, with K set to 32, and scrambler turned off in both FPGA and ADC. Programming the ADC using GUI provided with EVM. I noticed the polarity inversion of JESD lanes on ADC12J400EVM and accounted for it in the FPGA. 

Any ideas what might be the cause of this discrepancy?

Thanks,

Ranjeet

This is what I observe:

Lane0:  0xFF0 0x021 0xFF0 0x043 0x0F0 T: 0x5

Lane1:  0xEE1 0x121 0xEE1 0x143 0x0E1 T: 0x5

Lane2:  0xDD2 0x221 0xDD2 0x243 0x0D2 T: 0x5

Lane3:  0xCC3 0x321 0xCC3 0x343 0x0C3 T: 0x5

Lane4:  0xBB4 0x421 0xBB4 0x443 0x0B4 T: 0x5

Lane5:  0x996 0x621 0x996 0x643 0x096 T: 0x5

Lane6:  0xAA5 0x521 0xAA5 0x543 0x0A5 T: 0x5

Lane7:  0x887 0x721 0x887 0x743 0x087 T: 0x5

According to the datasheet, this is the expected pattern:

Table 37. Short Transport Test Pattern