Hi, everyone,
I'm developing a AFE5809 + FPGA + Application SoC system.
The FPGA relies on the sync word in the LVDS channels of AFE5809 to function properly so I can not turn the demodulator off.
Is it possible to leave the demodulator enabled but let it pass ADC data through?
I'm thinking about:
set M=1; MODULATE_BYPASS 0x0A[14]=0; OUTPUT_CHANNEL_SEL 0x0A[11]=0; DWN_CNV_BYPASS 0x0A[2]=1
And set coefficient ram to a single impulse, and set profile RAM to a unit gain.
then ADC data will by pass down conversion, while decimation filter and decimation do nothing.
Is this correct?
So basically what I'm asking is, when down conversion is bypassed, is the ADC data passed unchanged to the I channel while Q channel is always 0?