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ADS8505 intermediate data bus latches

Michael Boyle
Prodigy 70 points
Other Parts Discussed in Thread: ADS8505

I am using an ADS8505 convertor and there is a reference at the bottom of page 16 of the data sheet regarding intermediate latches for the data bus.  Can you please explain the issue here?  I have inherited this design and It may take me a while to investigate what data bus activity may be going on during the time the convertor is doing it's conversions.  The data bus has three 8505s and two DAC712 DACs.  I am going to have to investigate the code of some programmable logic to understand how the data bus is being used.  It may turn out that the data bus is HI-Z during the conversion times.  Can you please explain how this issue may manifest itself in the converted data if the bus is either active or Hi-Z?

Thank you for your time.

Best regards,

Mike Boyle

  • 0
    TI__Guru 55466 points

    Hi Michael,

    The parallel interface output is active when R/C is high and CS is low; and the interface will tri-state during any other combination of CS/RC.

    Page 16 of the datasheet recommends the intermediate interface latches to isolate the ADC for the case where the parallel bus is to be active with other devices during conversion phase of the ADC.  The concern is that fast transients due to the interface switching may couple through the substrate of the device to the analog circuitry causing degradation on the conversion results.  This would manifest primarily as a degradation on the noise performance of the ADC (degradation on transition noise performance or SNR performance).

    Please let me know if you have additional questions,

    Best Regards,

    Luis