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ADS1147: Do any SPI "Sync" commands actually work?

Other Parts Discussed in Thread: ADS1147

The ADS1147 datasheet, SBAS453F - revised 2012, in the "digital filter reset" section on page 29, states:

Apart from the RESET command and the RESET pin,

the digital filter is reset automatically when either a

write operation to the MUX0, VBIAS, MUX1, or SYS0

registers is performed, when a SYNC command is

issued, or the START pin is taken high.

I am not seeing this behavior when writing SYNC commands or when writing registers to my ADS1147, but I am clearly writing registers correctly as evidenced by changing the data rate and by the DOUT/DRDY mode working properly on the DOUT pin and by getting correct data readings.

Instead, whatever conversion is in progress seems to complete and set DOUT low (to the "Ready" state) early.

Did I miss something?

My Circuit ties START high, DRDY is no-connect, and I am dropping CS before writing a NOOP to ensure DOUT is functioning as the DRDY output.

  • Eric,


    I've never specifically tested these reset conditions myself, but I'm quite sure that the datasheet is correct. From other customer's use of this device, it should work this way, or a lot of the multiplexed channel applications that I've seen would have problems with operation. In a write to the device for one of the MUX0, VBIAS, MUX1, or SYS0 registers, it shouldn't complete the conversion, it should change the setting and start the new conversion.

    I would start by looking at the communications with a logic analyzer and doing a simple test. I would simply let the part run, continuously converting, and observe the /DRDY pin. Then, issue a SYNC command and see how the /DRDY timing is affected. If you have something like a Saleae logic analyzer, I can take the data and use their software to look at the communication. I would record /CS, DIN, DOUT, SCLK, and /DRDY.

    If this works, I would look at the /DRDY behavior after a write to the first four registers. I should be something different than the previous register contents. I think that the device does check to see if the state changes from the register write.

    Other than that, do you have any scope photos to show that the timing isn't changing after the write or the SYNC? If you can get a shot, please post it or even better post the data from a Saleae logic analyzer. I'm not certain what other formats I can take, so some sort of screen shot might be best.


    Joseph Wu
  • Thanks....

    Indeed, it would help very much if my code ensured that the CS (Chip Select) pin was low when I wrote the SPI data....I found that out once I started cycling channels...

    Once that issue is taken care of, the chip works as advertised.

    Eric Christenson

    P.S. The code on my CPU got buggy because I need to be able to interrupt communications on the port asynchronously for a higher priority device on the same port, and I had no code review to pick up that the chip deselect at the end of the routine that writes to a register did not have a corresponding chip select at the beginning, thus asking for trouble! I'm re-organizing and re-writing that code today.


    P.P.S. The datasheet says chip restarts conversion on EVERY write to those registers, change or not. That's not unreasonable.

    P.P.P.S. Saleae logic analyzer? I'm using MPLAB REAL ICE and a two-channel digital scope, and mainly checking on the CS line.
  • Eric,


    Thanks for the reply. I'm glad you got the code working. If you have any other questions, feel free to post back.

    BTW, I do like the Saleae logic analyzer. Along with being able to make coarse analog measurements, it has a pretty good software package to read the signals. I will say that some of the data files are pretty long, but there's not much to be done with that.


    Joseph Wu