DAC - Understanding Settling Time & Update Rate

Hi Utpal,
Let me answer your questions.

1) How does Update Rate get mapped with DAC?
[RP]: In this case, the settling time of DAC output will dominate the output update time.
Assuming SPI SCLK is clocking at 50MHz and you need minimum 32 clocks to write and minimum SYNC high time, SPI delay is (20X32+35) ns = 0.675usec. The DAC output settling is specified to 8usec.
Therefore, the total update time is 8.675usec (DAC settling + SPI delay) for zero to full scale step. The internal track and hold time is already included in DAC settling for this case. Note that the above analysis is based on generating square wave output from a precision DAC. Adding more steps in this transition is going to slow down the update time further.

2) Does it imply "how fast" a DAC can "produce" analogue output from input digital code?
[RP]: No, as described above it means how fast the data can be written to the DAC.

3) If that is so, does the Settling Time have any effect on the Update Rate?
[RP]: Yes, the settling time will dominate the update rate in this case.

4) DAC60004 family talks about 50 MHz SPI compatible interface. Am I to assume that the Update Rate = 50 MSPS (which might be so considering part selection tool in TI)
[RP]: No, the output update rate would have to include DAC settling time as shown above

5) Settling Time for DAC60004 = 8 uSec (max.). Is it right to say max. n. of samples those can be output = 1 / 8 uSec = 125 kSPS? If true, it does not meet with 50 MSPS value.
[RP]: Yes, you are right, the output update rate is close to 8usec for a full scale step.

If you want to learn more about DAC speed limitation please visit

e2e.ti.com/.../dac-essentials-understanding-your-dac-39-s-speed-limit

Best Regards,
Rahul Prakash

Hi Utpal,

Please see my responses

1) With settling time (max.) of 8 uS and SPI delay of 0.675 uS, would it be correct to say that the highest frequency of output analogue signal; for faithful reproduced signal; is (1 / 8.675 uS) / 2 = 57.7 kHz?

[RP]: No, this will be valid if the DAC is stepping from 1/4*Full-Scale-Range to 3/4*Full-Scale- - see settling time spec. This is not the fastest frequency for 2-code step. if the DAC is only stepping by 1 LSB the update frequency can be higher since the small signal settling for DAC is much faster..

2) Referring your comment "Note that the above analysis is based on generating square wave output from a precision DAC. Adding more steps in this transition is going to slow down the update time further.":
Do you mean the worst code transition of 000000000000 ==> 111111111111? Also adding steps would undoubtedly slow down update rate but if my statement 1 holds right, we are good to go for max. output signal frequency of 57 kHz.

[RP]: See above.

3) Also, please see the screen shot below. Why update rate is then specified as 50 MSPS for this family?

[RP]: We are referring to input update rate for the DAC i.e. SPI SCLK speed in this table.

Best Regards,

Rahul Prakash