Hello,
There is an explanation about output compliance range in DAC5681Z as below.
>>The lower limit of the output compliance is determined by the CMOS process. Exceeding this limit may result in transistor breakdown, resulting in reduced reliability of the DAC5681Z device. The upper limit of the output compliance is determined by the load resistors and full-scale output current. Exceeding the upper limit adversely affects distortion performance and integral nonlinearity.
1) I think above AVDD+0.5V, distortion reason is to work ESD diode. Is my understanding correct?
2) I couldn't imagine why AVDD-0.5V may result in transistor breakdown. Could you give me some explanation why this happens?
Best regards,
Toshihiro Watanabe