VSP 2582

Dear Antony,

Thank you for posting your request with the forum.

As a first step, could you please send the schematic and block diagram of the system. Possible issues are

      Currently CLPOB connected to VCC & CLPDM connected to Ground. - Verify with the VSP2582 data sheet, this may cause an issue with device operation because it never sees any of the pixles as imaging. Dependind on the register settings for polarity, be sure thises conditions correspond to not active condition. In default conditions, CLPOB is active LOW, so it should be tied HIGH. RIght now, the device thinks all the pixles are optical black and there are no imaging pixels to digigtize.

     Couild you also please send the timing to verify the switching is occurng proprly and the analog out put switch is fast enough for the clock rate being used.

     Finally, could you please send the register settings,

Regards,

Werner Metz

Texas Instruments, wmetz@ti.com

Dear Warner

I  have sent you the schematics & PPT  by mail. Please look into that

Regards

Noel

Noel,

Thank you for sending the schematics and the TI .ppt.

1) In VSP2582 data sheet, page 16, Register description for CLK-Pol-Ctrl register. Note the default is active low for both CLPDM and CLPOB. Please ensure that both of these signals are tied high. If they are low, then none of the pixels are recognized as imaging pixels and are not digitized.

2) What are you using for the analog switch to mux the high and low signals? We would recommend a high mux such as TS5A3359DCUR or similar to ensure switcing speed is high enough.

3) The digital outputs are not strong enough to drive an LED directly. If you are arechanging the input values very slowly (essentially statically), then you can use a multi-meter to measure each Data Out line independently. The best method is use either a logic analyzer or an FPGA to capture the digital output data.

Regards,

Werner Metz

Hi Werner

I am out of office for 2 weeks

1. I have tested the ADC by connecting the CLPDM & CLPOB pins to high(3V) and the ADC output data (D0-D11) does not seems to be changing

2. I am using  TS5A3159 for the analog switch, and observed the voltage variation

3. OK. Currently i do not have the logic analyser, but i have observed the data output of ADC  (D0- D11) seen through the DSO (four channel) but no change observed for the variation of the analog input.

I expect further assistance

Regards

Noel

Noel,

The device should work with the default register settings. If you have not changed these, there is no need to send them. If bit D4, address 002h is somehow set to 1, then this would disable the outputs. Default at power up is set to 0, outputs enabled.

There are only a couple of possibilites left. For these tests, ground the inputs (J1, J2 and/or J3 on your schematic). You should be able to monitor the LSB's (B0-B3) with your 4 channel DSO and observe ranfom fluctuations.

1. Can you send a scope trace of the signals CCDIN, ADCCK, SHP and SHD (similar to Figure 1, page 7 of data sheet). I want to verify that the waveforms meet the timing specifications shown. In particular, ensure that the low levels of SHP and SHD do not overlap. How are SHP and SHD derived from ADCCK? All should be the same frequency, but shifted phase as shown in the diagram.

2. Verify there is power to Vdd, pin 11. This is the power supply for digital data output. Similarly, verify that pin 12, DGND is grounded. This is the ground for the digital outputs.

3. Verify there is no loadng on the digital output lines. An earlier mail stated you had LED's as indicators. These are likely too heavy a load. Please remove these if possible and observe if there is actrivity on the digital output lines.

4. What is the state of the SLOAD pin? it should be HIGH if you are not programming the device.

5. Finally, has this been observed across multiple devices? Want to check if the device is damaged or inert.

Regards,

Werner Metz

Dear Werner

Thanks for your reply.

I think i have not conveyed my problem correctly.  The digital output is coming  (D0-D11) but the output does not change in accordance to the input analog voltage when the voltage is changed.( CCDIN voltage  given by the circuit suggested by TI and adjusted by using the potentiometer)

Regards

Noel

Noel.

To restate the problem, you do have digital outputs on D0-D11, but they are not responding as expected with change in input voltage.

Then I will still need to see item 1, the four traces for CCDIN, ADCCK, SHP and SHD. The signal which is digitized is the difference between the input voltages at SHP rising edge and SHD rising edge. (see attached .ppt). The expecattion is that the voltage at SHP is more positive than the voltage at SHD. This is because with a CCD, the output at SHD is more negative with more photoelectrons ( more light) in a pixel.

Also, note that the more negative the difference between voltage at SHP and the voltage at SHD, the _higher_ the digitized value.

The second question is, how are you measuring the output with only four leads on the DSO? If you are not measuring all 12 output lines simultaneously it can be difficult to infer the correct output value.

              Which bits are you measuring?

              Can you supply a table/graph showing the input voltage (difference between SHP (rising edge) - SHD(rising edge) and the output you are measuring?

Regards,

Werner Metz