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ADS1248 Ain common mode range with PGA gain = 1, AVss = DGND = 0V, AVdd = DVdd = 3.3V

Richard Chaney
Intellectual 310 points

Hi,

I read all of the statements and equation concerning common mode in the datasheet.  In my design, I thought the lower common mode limit would be AVss + 0.1V, and the upper limit to be AVdd -0.1V.  I have run some tests, and it seems that this is not true!  Are my limits incorrect?

Thanks,

Richard

  • 0
    TI__Guru* 98015 points

    Richard,



    Yes, the AVSS+0.1V to AVDD-0.1V should be fine with PGA=1.

    Can you share a basic schematic and other register settings? It helps to have the input voltage value measured back and the output raw data (in hex or decimal).


    Joseph Wu